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labs:structural_verilog [2019/09/24 15:40] jgoeders [Exercise #1: Implement Logic Functions in Structural SystemVerilog] |
labs:structural_verilog [2020/04/20 14:35] (current) nelson [Exercise #2: Implement Logic Functions in Structural SystemVerilog] |
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| ===== Exercises ===== | ===== Exercises ===== | ||
| - | ==== Exercise #1: Implement Logic Functions in Structural SystemVerilog ==== | + | ==== Exercise #1: Creating a Vivado Project ==== |
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| + | Many software tools are needed to convert your SystemVerilog file into a configuration bit file that you can download onto an FPGA device. We will be using a set of tools called **Vivado** developed by Xilinx, the manufacturer of the FPGA devices in the lab. You will use Vivado throughout the rest of the semester. | ||
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| + | - Create a new Vivado project by following the instructions in the [[tutorials:vivado_project_setup]] tutorial. __Make sure you follow the steps in red to properly configure the error messages in your project.__ | ||
| + | - Now, create a new SystemVerilog file to hold a module by following the instructions in the [[tutorials:creating_a_new_module]] tutorial. Your module will be called "FourFunctions". Do not add any ports to it in this exercise, you just want an empty module definition. | ||
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| + | ==== Exercise #2: Implement Logic Functions in Structural SystemVerilog ==== | ||
| In this exercise you will create the //structural// SystemVerilog description of four logic functions. Note that you must use structural SystemVerilog rather than Dataflow SystemVerilog to complete this assignment. Follow the steps below to begin this exercise. | In this exercise you will create the //structural// SystemVerilog description of four logic functions. Note that you must use structural SystemVerilog rather than Dataflow SystemVerilog to complete this assignment. Follow the steps below to begin this exercise. | ||
| - | - Open up your favorite **text** editor such as VS Code, Notepad++, notepad, emacs, etc. Note that your editor must save the file as "text" - programs such as Microsoft Word do not by default save files as text. | + | - Open up the FourFunctions.sv module you created in Exercise #1 by double-clicking it in the figure you just saw above. |
| - | - Create an empty file named **FourFunctions.sv** (note the extension ".sv" indicating a SystemVerilog file). This will be the text file that contains the SystemVerilog file for your lab. | + | - Start your file by creating a **header** in your SystemVerilog file that conforms to this class's [[:verilog_coding_standards]]. If Vivado has pre-populated the file with header information you are free to remove that or modify it (do not delete the first line that contains `timescale 1ns / 1ps, however. Either way, your design must have a **header** that conforms to the class's [[:verilog_coding_standards]] |
| - | - Start your file by creating a **header** in your SystemVerilog file that conforms to this class's [[:verilog_coding_standards]]. | + | - NOTE: the coding standards are very specific on how to declare the inputs and outputs of modules. If you read carefully, you will note that they require the inclusion of the word "wire" in certain places. This is not reflected in the textbook examples. The need to include this is due to specific requirements of Vivado when the `default_nettype none macro directive is included.) |
| - | - Define a module named "FourFunctions" with the following ports. Make sure to match everything described below exactly (including the port names). | + | - Now, define a module named "FourFunctions" with the following ports. Make sure to match everything described below exactly (including the port names). |
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| + | NOTE: if you are fuzzy on module declarations, consult the textbook. In particular, review Sections 8.3, 8.4, and 8.6.1 in the textbook. And, just remember that due to our using Vivado, you also need to include the word "wire" in certain places. Consult the [[:verilog_coding_standards]] for details on that. | ||
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| + | Finaly, at this point remember there is no reason to get creative - just copy the structure and syntax (including indentation) of the code examples in the book sections noted. And, carefully follow the coding standard. This goes for this lab as well as all future labs. | ||
| **Module Name**: FourFunctions | **Module Name**: FourFunctions | ||
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| * **O1**: O1 = AC+A'B | * **O1**: O1 = AC+A'B | ||
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| * **O2**: O2 = (A+C')(BC) | * **O2**: O2 = (A+C')(BC) | ||
| - | * **O3**: The logic function in the textbook Figure 5.2 (Page 45) | ||
| - | * **O4**: The logic function in the textbook Figure 5.25a (Page 58) //Make sure you look carefully in the end of the chapter to find the correct circuit diagram -- it is subfigure **a** (the one on the left).// | ||
| - | You do not need to minimize these functions, just implement the logic functions directly using basic gates (AND, OR, NOT, etc). | + | * **O3**: The logic function below: |
| - | Complete your initial attempt at the SystemVerilog for these four functions before proceeding. In the next exercise you will have the opportunity to find and correct errors when you analyze the syntax and behavior of your SystemVerilog. | + | {{:labs:simpleschem.png?400|Function for O3}} |
| - | **Exercise 1 Pass-off:** There is no pass off for this exercise.\\ \\ | + | * **O4**: The logic function below: |
| + | {{:labs:hwb.png?300|Function for O4}} | ||
| + | If these functions require intermediate signals (signals that are not module ports), you will need to declare them using the 'logic' keyword (see text for details). Also, choose meaninful names or (probably better yet) put a comment above them to tel what they are used for. | ||
| - | ==== Exercise #2: Creating a Vivado Project ==== | + | You do not need to minimize these functions, just implement the logic functions directly using basic gates (AND, NAND, OR, NOR, NOT, etc). |
| - | Many software tools are needed to convert your SystemVerilog file into a configuration bit file that you can download onto an FPGA device. We will be using a set of tools called **Vivado** developed by Xilinx, the manufacturer of the FPGA devices in the lab. You will use Vivado throughout the rest of the semester. | + | As you type and save your SystemVerilog code, Vivado will identify syntax errors in the code. Edit the code until there are no syntax errors. |
| - | + | ||
| - | - Create a new Vivado project by following the instructions in the [[tutorials:vivado_project_setup]] tutorial. __Make sure you follow the steps in red to properly configure the error messages in your project.__ | + | |
| - | - Add the SystemVerilog file you created in exercise 1 to your project by following the [[tutorials:creating_a_new_module#adding_a_previously_created_module|adding a design file]] section of the Adding a SystemVerilog Module tutorial. When you add your SystemVerilog file, the Vivado tools will perform basic syntax checking on the file. Any syntax errors will be highlighted and summarized in the messages tab. | + | |
| - | - Fix any syntax errors in your code. | + | |
| With no syntax errors in your HDL code you can perform **elaboration** and generate a notional schematic of the circuit. Follow the [[tutorials:viewing_design_elaboration]] tutorial to view a schematic of your code. | With no syntax errors in your HDL code you can perform **elaboration** and generate a notional schematic of the circuit. Follow the [[tutorials:viewing_design_elaboration]] tutorial to view a schematic of your code. | ||
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| Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | ||
| - | **Exercise 2 Pass-off:** Show a TA your circuit schematic. Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\ | + | **Exercise 2 Pass-off:** Review your code with a TA as well as your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\ |
| /* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete. | /* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete. | ||
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| ==== Exercise #3: SystemVerilog Simulation ==== | ==== Exercise #3: SystemVerilog Simulation ==== | ||
| - | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. The greater skill you have at using these simulation tools, the easier and more successful you will be in all future labs. | + | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. |
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| + | Why is it so important to learn to use the simulator? Finding errors in your design in simulation may take seconds or minutes, whereas finding those same errors in your physical circuit after it is running on the FPGA board may take hours. !!! The greater skill you have at using these simulation tools, the easier and more successful you will be in all future labs. | ||
| Complete the following steps for this exercise: | Complete the following steps for this exercise: | ||
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| During this exercise you will translate your SystemVerilog HDL file into an actual digital circuit that can operate on the FPGA device. There are three specific steps you must complete in order to perform this translation. These steps include: | During this exercise you will translate your SystemVerilog HDL file into an actual digital circuit that can operate on the FPGA device. There are three specific steps you must complete in order to perform this translation. These steps include: | ||
| - HDL Synthesis, | - HDL Synthesis, | ||
| - | - Implemetnation, and | + | - Implementation, and |
| - Bitfile Generation | - Bitfile Generation | ||
| This exercise will describe each of these steps and guide you through the process of completing these steps for your design. | This exercise will describe each of these steps and guide you through the process of completing these steps for your design. | ||
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| For example, this table indicates that the "A" input to your logic circuit should be mapped to pin "M13" of the FPGA on the NEXYS 4 board. The table also indicates that the "M13" pin is attached to Switch 2 on the board. | For example, this table indicates that the "A" input to your logic circuit should be mapped to pin "M13" of the FPGA on the NEXYS 4 board. The table also indicates that the "M13" pin is attached to Switch 2 on the board. | ||
| To make an XDC file, follow the instructions in the [[tutorials:making_an_xdc_file]] tutorial. | To make an XDC file, follow the instructions in the [[tutorials:making_an_xdc_file]] tutorial. | ||
| - | Your constraints file should have seven different constraint commands, one for each of the inputs and outputs of your circuit. | + | Your constraints file should have seven different constraint commands, one for each of the inputs and outputs of your circuit. Remember that it is easier to include the Master XDC File (found on the bar on the left) and uncomment the lines you need rather than making the file yourself. |
| <color red>Include the text of your XDC file in your laboratory report.</color> | <color red>Include the text of your XDC file in your laboratory report.</color> | ||
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| HDL synthesis (also called logic synthesis) is the process of converting your HDL code into an intermediate circuit netlist of gates and logic primitives. Synthesis tools are complex and use a lot of sophisticated algorithms to perform this translation. Follow the [[tutorials:synthesis]] tutorial to run the synthesis tool on your design. | HDL synthesis (also called logic synthesis) is the process of converting your HDL code into an intermediate circuit netlist of gates and logic primitives. Synthesis tools are complex and use a lot of sophisticated algorithms to perform this translation. Follow the [[tutorials:synthesis]] tutorial to run the synthesis tool on your design. | ||
| - | During the synthesis process you may encounter synthesis warnings from the synthesis tool. It is common to receive many warnings especially for large circuits. It is essential that you review the warnings of the synthesis step before proceeding to the implementation step. In most cases these warnings can be ignored but it is essential to review them as subtle warnings in the logic synthesis tool are often are the cause of complex problems later in the design process. | + | During the synthesis process you may encounter synthesis warnings from the synthesis tool. It is common to receive many warnings especially for large circuits. It is essential that you review the warnings of the synthesis step before proceeding to the implementation step. In most cases these warnings can be ignored but it is essential to review them as subtle warnings in the logic synthesis tool are often are the cause of complex problems later in the design process. And, like with the comment about simulation you saw earlier, errors that you overlook because you ignore the synthesis warnings may take a LONG time to figure out. The errors and warnings are there for a reason - don't proceed until you have checked them - it will save you time. |
| <color red>List the warnings in your synthesis report.</color> State that there were no warnings if none show up. Warnings can be found in the **Messages** tab at the bottom of the screen. They can also be found in the **Reports** tab at the bottom of the screen under **Vivado Synthesis Report**. | <color red>List the warnings in your synthesis report.</color> State that there were no warnings if none show up. Warnings can be found in the **Messages** tab at the bottom of the screen. They can also be found in the **Reports** tab at the bottom of the screen under **Vivado Synthesis Report**. | ||
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| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
| - | Here are some ideas for personal exploration in this laboratory: | + | Choose one of the following tasks to do as a personal exploration: |
| - | * Compare and contrast the difference between the circuit you specified in your original SystemVerilog file and the schematic that is generated from your file. | + | * Compare and contrast the difference between the circuit you specified in your original SystemVerilog file and the schematic that is generated from your file. Are there differences? What is similar and what is different? |
| * Add an additional fifth logic function to your SystemVerilog file and synthesize it using the steps described in the laboratory instructions. | * Add an additional fifth logic function to your SystemVerilog file and synthesize it using the steps described in the laboratory instructions. | ||
| - | * Explore a variety of different features and aids in the simulation tool and summarize them. | ||
| - | * Explore various options available in the Vivado design suite and summarize what they do. | ||
| <color red>Describe your personal exploration activities</color> | <color red>Describe your personal exploration activities</color> | ||
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| [[labs:ta:structural_verilog|TA Notes and Feedback]] | [[labs:ta:structural_verilog|TA Notes and Feedback]] | ||
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| + | [[testDev]] | ||
