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labs:stopwatch [2020/04/28 16:43] nelson [Final Passoff] |
labs:stopwatch [2020/05/18 11:18] (current) nelson [Personal Exploration] |
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| * Turn on the appropriate decimal point. | * Turn on the appropriate decimal point. | ||
| * **Note:** The CPU_RESETN button is active-low. This means it behaves differently than the other buttons you have used: it is a ''0'' when pressed and a ''1'' otherwise. You will need to invert the signal when connecting it to your ''stopwatch'' and ''SevenSegmentControl'' modules. | * **Note:** The CPU_RESETN button is active-low. This means it behaves differently than the other buttons you have used: it is a ''0'' when pressed and a ''1'' otherwise. You will need to invert the signal when connecting it to your ''stopwatch'' and ''SevenSegmentControl'' modules. | ||
| - | * In case you didn't notice, the CPU_RESETN button is active-low. Think about what that means before you continue. Failing to grasp the significance of this is one of the biggest pitfalls of this lab. | ||
| Be sure to include an appropriate constraints file: | Be sure to include an appropriate constraints file: | ||
| * **Note:** For this lab, and all subsequent labs that use the ''clk'' pin, you should also uncomment two lines near the top that refer to the clock. One connects the clock, the line after it tells informs Vivado that the clock runs at 100MHz. | * **Note:** For this lab, and all subsequent labs that use the ''clk'' pin, you should also uncomment two lines near the top that refer to the clock. One connects the clock, the line after it tells informs Vivado that the clock runs at 100MHz. | ||
| + | ===== Final Passoff===== | ||
| + | Show the TAs your stopwatch working on the board. | ||
| - | **Pass-off:** Show the TAs your stopwatch working on the board. | + | =====Final Questions===== |
| - | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite. (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). </color> |
| + | <color red>How many hours did you spend on this lab?</color> | ||
| - | =====Final Passoff===== | + | <color red>Describe any problems or challenges you had with the lab. </color> |
| - | <color green> | + | |
| - | Attach a video (narrated) describing how your design operates. Time it to show that it really is counting seconds at the correct rate. Show how you can clear it at well and how you can start and stop it at will. Also, describe how long it will take for the counter to completely roll over and show that happening if it is feasible to do so. | + | |
| - | </color> | + | |
| - | =====Final Questions===== | + | /* |
| - | <color red> | + | =====Personal Exploration===== |
| - | How long (in hours) did you work on this lab? | + | Here are some ideas for personal exploration in this laboratory: |
| - | </color> | + | * Use additional switches to make your stopwatch run faster or slower than real-time. |
| + | * Modify your design to work as a countdown timer when sw1 is high, and a count-up timer when sw0 is low. | ||
| - | <color red> | + | <color red>Describe your personal exploration.</color> |
| - | List the pitfalls you encountered in this lab. What made it take longer than it should have (in your mind)? | + | */ |
| - | </color> | + | |
