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labs:stopwatch [2020/03/04 08:55] nelson [Exercise 2: Stopwatch Module] |
labs:stopwatch [2020/05/18 11:18] (current) nelson [Personal Exploration] |
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| * Create a Vivado project. | * Create a Vivado project. | ||
| * Write the SystemVerilog for the ''mod_counter'' module. | * Write the SystemVerilog for the ''mod_counter'' module. | ||
| + | * NOTE: the vast majority (>90%?) of students write the logic for their ''rolling_over'' wrong the first time. Why? Go re-read the description for this signal above a third time. Exactly what is the logic condition for this signal? Does it involve the 'clk' signal and a register or is it purely combinational logic? If you put the code to generate this signal this inside an ''always_ff'' block will it generate a register or will it generate combinational logic? What is it that you really want? | ||
| * Create a tcl simulation script, and verify that your counter is working. Make sure your simulation is thorough; for example, check that the counter only counts when ''increment'' is high, and that the ''rolling_over'' output is high only in the appropriate condition. Also, don't forget to do the Tcl file in this general order: a) set up the clocking, b) reset the design and simulate a few cycles, and then c) exercise the rest of your counter functionality. | * Create a tcl simulation script, and verify that your counter is working. Make sure your simulation is thorough; for example, check that the counter only counts when ''increment'' is high, and that the ''rolling_over'' output is high only in the appropriate condition. Also, don't forget to do the Tcl file in this general order: a) set up the clocking, b) reset the design and simulate a few cycles, and then c) exercise the rest of your counter functionality. | ||
| Line 83: | Line 84: | ||
| Some things to remember: | Some things to remember: | ||
| - You will need to declare local signals for those wires in the diagram below that are not input or output signals. | - You will need to declare local signals for those wires in the diagram below that are not input or output signals. | ||
| - | - Note that the your ''timer'' module output ('count') is not tied to anything. You will still need to declare a local signal for it to wire up to the ''timer'' module, but that signal will not drive anything in your ''stopwatch'' module. | + | - Note that the your ''timer'' module output ('count') is not tied to anything. You will still need to declare a local signal for it to wire up to the ''timer'' module, but that signal will not connect to anything else in your ''stopwatch'' module. |
| ^ Module Name = stopwatch ^^^^ | ^ Module Name = stopwatch ^^^^ | ||
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| * The stopwatch only runs when the ''run'' input is high. | * The stopwatch only runs when the ''run'' input is high. | ||
| * The digits roll over correctly. | * The digits roll over correctly. | ||
| + | * The rest works after it has counted for some time. | ||
| <color #ed1c24>Include your Tcl simulation script in your lab report.</color> | <color #ed1c24>Include your Tcl simulation script in your lab report.</color> | ||
| Line 129: | Line 131: | ||
| Be sure to include an appropriate constraints file: | Be sure to include an appropriate constraints file: | ||
| - | * **Note:** For this lab, and all subsequent labs that use the ''clk'' pin, you should also include the line from the constraints file immediately below the clk pin contraint (''create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];''). This informs Vivado that the clock runs at 100MHz. | + | * **Note:** For this lab, and all subsequent labs that use the ''clk'' pin, you should also uncomment two lines near the top that refer to the clock. One connects the clock, the line after it tells informs Vivado that the clock runs at 100MHz. |
| + | ===== Final Passoff===== | ||
| + | Show the TAs your stopwatch working on the board. | ||
| - | **Pass-off:** Show the TAs your stopwatch working on the board. | + | =====Final Questions===== |
| - | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite. (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). </color> |
| + | <color red>How many hours did you spend on this lab?</color> | ||
| + | <color red>Describe any problems or challenges you had with the lab. </color> | ||
| + | |||
| + | /* | ||
| =====Personal Exploration===== | =====Personal Exploration===== | ||
| Here are some ideas for personal exploration in this laboratory: | Here are some ideas for personal exploration in this laboratory: | ||
| * Use additional switches to make your stopwatch run faster or slower than real-time. | * Use additional switches to make your stopwatch run faster or slower than real-time. | ||
| * Modify your design to work as a countdown timer when sw1 is high, and a count-up timer when sw0 is low. | * Modify your design to work as a countdown timer when sw1 is high, and a count-up timer when sw0 is low. | ||
| + | |||
| + | <color red>Describe your personal exploration.</color> | ||
| + | */ | ||
