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labs:sp20_uat [2020/06/02 13:26] nelson [Exercise #3 - Top-Level TX Circuit] |
labs:sp20_uat [2020/06/02 13:28] (current) nelson |
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| <color red>Please provide any suggestions for improving this lab in the future.</color> | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| - | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | <color red>Upload your tx.sv SystemVerilog module to Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). |
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| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
