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labs:sp20_uat [2020/06/02 13:21] nelson [Exercise #3 - Top-Level TX Circuit] |
labs:sp20_uat [2020/06/02 13:28] (current) nelson |
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| After completing your .xdc file, proceed to generate your bitstream. | After completing your .xdc file, proceed to generate your bitstream. | ||
| - | <color red>Upload and describe a summary of your synthesis warnings</color>. | + | <color red> |
| + | Attach a copy of and then explain in word any ERRORS or CRITICAL WARNINGS that are in either the synthesis report from above. For each one, explain the following: What does this ERROR or CRITICAL WARNING refer to and do you understand why was it flagged? Is it OK or not for you to ignore it and assume the design will work in hardware (and if so, why)? Please explain. | ||
| + | </color> | ||
| **Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\ | **Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\ | ||
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| <color red>Please provide any suggestions for improving this lab in the future.</color> | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| - | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | <color red>Upload your tx.sv SystemVerilog module to Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). |
| /* | /* | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
