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labs:sp20_uar [2020/06/10 16:20] nelson |
labs:sp20_uar [2020/06/10 17:08] (current) nelson [Exercise #3 - Test It in hardware] |
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| After creating your rx module, create a TCL file and simulate | After creating your rx module, create a TCL file and simulate | ||
| - | your receiver module to make sure that there are no major errors. Then simulate | + | your receiver module to make sure that there are no major errors. |
| + | |||
| + | <color red> Attach a copy of your Tcl file and a | ||
| + | screenshot of your working simulation to Learning Suite.</color>\\ \\ | ||
| + | |||
| + | Then simulate | ||
| your module with the following testbench file: | your module with the following testbench file: | ||
| {{ :labs:tb_rx.sv |}} | {{ :labs:tb_rx.sv |}} | ||
| - | <color red>Attach a copy of the console output from the testbench simulation in your lab report</color> | + | <color red>Attach a copy of your receiver design's SystemVerilog code to your lab report, in PDF.</color> |
| + | |||
| + | <color red>Attach a copy of the console output from the testbench simulation in your lab report, showing no errors.</color> | ||
| - | <color red>Include the SystemVerilog code for your receiver module in your report</color> | ||
| - | **Exercise 2 Pass-off:** <color red> Attach a copy of your Tcl file and a | ||
| - | screenshot of your working simulation to Learning Suite.</color>\\ \\ | ||
| ==== Exercise #3 - Test It in hardware ==== | ==== Exercise #3 - Test It in hardware ==== | ||
| - | In this exercise you are going to simulate a transmitter/receiver pair as shown in the figure below. | + | In this exercise you are going to test your receiver in hardware. |
| /*{{:labs:lab_11:img_0065.jpg?900|}} | /*{{:labs:lab_11:img_0065.jpg?900|}} | ||
| Line 132: | Line 136: | ||
| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
| - | | reset | Input | 1 | Reset signal | | + | | reset | Input | 1 | Reset signal, wired to a button | |
| - | | Receive | Output | 1 | Receive handshake: character has been received by UART | | + | | ser_in | Input | 1 | The serial signal coming from putty, wired to the receive rx_in signal on the FPGA | |
| - | | rxData | Output | 8 | Data that was received by receiver | | + | | Receive | Output | 1 | Receive handshake: character has been received by UART, tied to an LED | |
| - | | Received | Input | 1 | Receive handshake: host acknowledge receipt of character | | + | | Received | Input | 1 | Receive handshake: host acknowledge receipt of character, tied to a button | |
| - | | parityErr | Output | 1 | Parity error signal | | + | | rxData | Output | 8 | Data that was received by receiver, wired to LEDs | |
| - | | ser_in | Output | 1 | The serial signal coming from putty. | | + | | parityErr | Output | 1 | Parity error signal, wired out to an LED | |
| /*Inside this module, instance both your tx and rx modules. Then, connect the serial out | /*Inside this module, instance both your tx and rx modules. Then, connect the serial out | ||
| Line 145: | Line 149: | ||
| serially will be received by the receiver and presented back to the | serially will be received by the receiver and presented back to the | ||
| host as an 8-bit received data word. &/ | host as an 8-bit received data word. &/ | ||
| + | */ | ||
| + | |||
| + | Next, create a .xdc file which maps your top-level signal names to pins on the FPGA. In this case, your top level signal names don't match what is in the .xdc file so you will have to edit it to make them match like you have done in some previous labs. What to wire your top level ports to are given above. If any additional signals are needed, add them to the module and .xdc file as well. | ||
| + | |||
| + | Synthesize, implement, and generate a bitstream for your design. Test it in hardware with putty. In putty, anything you type will be sent down the line (make sure you have the baudrate, parity, etc all done correctly). It will NOT be mirrored to the putty screen but will go down the serial line where your receiver will receive it and display it on the LED's. Once your receiver has received a byte it should light up the Receive output to tell you that a new character has arrived. The handshaking will be that you assert the Received input (from a button) and your state machine will lower Receive and that is the end of the handshake. The received byte should be reflected on the LED's along with the parity error signal. | ||
| + | |||
| + | ===Some Thoughts on Testing=== | ||
| + | * Upon startup when your shift register has all 0's in it, what would you expect the value of your parityErr signal to be? Check it to be sure. | ||
| + | * Remember that after each character is received you must acknowledge it via handshaking using the Received button. | ||
| + | * This can be a difficult design to debug if it is not working. For example, if you set up putty and push a character and absolutely nothing happens, then what do you do? One common strategy would be to bring your state machine bits out to output pins and wire them to LED's. That way, if you FSM is just stuck in some state you will have a hint. | ||
| + | * The .xdc file for this design has been left wide open - it is easy to get confused about the role of Receive vs. Received and other signals. Carefully think through them until you are sure you understand what they are to do. | ||
| <color red>Include a copy of your top-level module in your laboratory | <color red>Include a copy of your top-level module in your laboratory | ||
| report</color> | report</color> | ||
| + | |||
| + | |||
| + | <color green> | ||
| + | Make a video demonstrating your final design and showing that, indeed, it does receive ASCII letters, punctuation, and digits and can display them on the LEDs. To test if the parity works, then change the parity in putty to even parity and show that you always get a parity error (even though the received character is good). | ||
| + | </color> | ||
| /*Now, write a Tcl file and do the simulation of your complete | /*Now, write a Tcl file and do the simulation of your complete | ||
