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labs:sp20_structural_verilog [2020/05/07 11:30] nelson [Exercise #3: SystemVerilog Simulation] |
labs:sp20_structural_verilog [2020/05/07 11:55] (current) nelson |
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| - It will install the needed C compiler for the simulator to work | - It will install the needed C compiler for the simulator to work | ||
| - | **If you are running Option #1 or Option #3 you should not have to do this.** | + | **If you are running Option #1 or Option #3 you should not have to do the above step.** |
| Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | ||
