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labs:sp20_structural_verilog [2020/05/04 12:25] nelson [Exercise #3: SystemVerilog Simulation] |
labs:sp20_structural_verilog [2020/05/07 11:55] (current) nelson |
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| ==== Exercise #3: SystemVerilog Simulation ==== | ==== Exercise #3: SystemVerilog Simulation ==== | ||
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| + | **If you are using Option #2: before beginning this step, you need to do the following just once to set up the tools:** | ||
| + | - Open a terminal in your Linux VM | ||
| + | - Type the following at a command prompt: sudo apt install gcc | ||
| + | - It will ask for your password | ||
| + | - It will install the needed C compiler for the simulator to work | ||
| + | |||
| + | **If you are running Option #1 or Option #3 you should not have to do the above step.** | ||
| Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | ||
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| Go read through the "Taming Vivado" information right now. | Go read through the "Taming Vivado" information right now. | ||
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| + | <color red> | ||
| + | What are the steps, in order, to fix a "simulator-is-wedged" problem? | ||
| + | </color> | ||
| <color red> | <color red> | ||
