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labs:sp20_structural_verilog [2020/05/04 12:09] nelson [Final Pass Off] |
labs:sp20_structural_verilog [2020/05/07 11:55] (current) nelson |
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| ==== Exercise #3: SystemVerilog Simulation ==== | ==== Exercise #3: SystemVerilog Simulation ==== | ||
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| + | **If you are using Option #2: before beginning this step, you need to do the following just once to set up the tools:** | ||
| + | - Open a terminal in your Linux VM | ||
| + | - Type the following at a command prompt: sudo apt install gcc | ||
| + | - It will ask for your password | ||
| + | - It will install the needed C compiler for the simulator to work | ||
| + | |||
| + | **If you are running Option #1 or Option #3 you should not have to do the above step.** | ||
| Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | ||
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| 3. Compare the resulting waveform with a truth table for your four functions. Verify that your simulation outputs match the expected outputs. If there are errors, fix your SystemVerilog file and simulate again until your circuit operates as intended. | 3. Compare the resulting waveform with a truth table for your four functions. Verify that your simulation outputs match the expected outputs. If there are errors, fix your SystemVerilog file and simulate again until your circuit operates as intended. | ||
| + | |||
| + | 4. What if it doesn't simulate correctly? It could be that (a) your code is wrong of (b) there is something wrong with the simulation. Yes, we have found times when you can get the simulator in a weird state, where re-simulating doesn't seem to reflect your most recent code changes. On the wiki, there is a item on the left side near the top called "Taming Vivado". If the simulator is just not making sense you may need to follow the steps in "Taming Vivado" to fix it. You should learn how to do those steps so you are not totally stuck when you can't get help from a TA. | ||
| + | |||
| + | Go read through the "Taming Vivado" information right now. | ||
| + | |||
| + | <color red> | ||
| + | What are the steps, in order, to fix a "simulator-is-wedged" problem? | ||
| + | </color> | ||
| <color red> | <color red> | ||
