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labs:sp20_structural_verilog [2020/04/08 16:37] nelson [Final Pass Off] |
labs:sp20_structural_verilog [2020/05/07 11:55] (current) nelson |
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| - | ====== Structural SystemVerilog ====== | + | ====== Sp20 - Structural SystemVerilog ====== |
| - | In this lab you will implement several logic functions using the SystemVerilog **HDL** (Hardware Description Language). You will simulate your SystemVerilog designs using commercial simulation tools and synthesize them into circuits that will be downloaded onto the NEXYS 4 board. | + | In this lab you will implement several logic functions using the |
| + | SystemVerilog **HDL** (Hardware Description Language). You will | ||
| + | simulate your SystemVerilog designs using commercial simulation tools | ||
| + | and synthesize them into circuits that will be downloaded onto the | ||
| + | NEXYS 4 board. | ||
| ===== Learning Outcomes ===== | ===== Learning Outcomes ===== | ||
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| ===== Exercises ===== | ===== Exercises ===== | ||
| - | ==== Exercise #1: Implement Logic Functions in Structural SystemVerilog ==== | + | ==== Exercise #1: Creating a Vivado Project ==== |
| + | |||
| + | Many software tools are needed to convert your SystemVerilog file into a configuration bit file that you can download onto an FPGA device. We will be using a set of tools called **Vivado** developed by Xilinx, the manufacturer of the FPGA devices in the lab. You will use Vivado throughout the rest of the semester. | ||
| + | |||
| + | - Create a new Vivado project by following the instructions in the [[tutorials:vivado_project_setup]] tutorial. __Make sure you follow the steps in red to properly configure the error messages in your project.__ | ||
| + | - Now, create a new SystemVerilog file to hold a module by following the instructions in the [[tutorials:creating_a_new_module]] tutorial. Your module will be called "FourFunctions". Do not add any ports to it in this exercise, you just want an empty module definition. | ||
| + | |||
| + | |||
| + | ==== Exercise #2: Implement Logic Functions in Structural SystemVerilog ==== | ||
| In this exercise you will create the //structural// SystemVerilog description of four logic functions. Note that you must use structural SystemVerilog rather than Dataflow SystemVerilog to complete this assignment. Follow the steps below to begin this exercise. | In this exercise you will create the //structural// SystemVerilog description of four logic functions. Note that you must use structural SystemVerilog rather than Dataflow SystemVerilog to complete this assignment. Follow the steps below to begin this exercise. | ||
| - | - Open up your favorite **text** editor such as VS Code, Notepad++, notepad, emacs, etc. Note that your editor must save the file as "text" - programs such as Microsoft Word do not by default save files as text files. | + | - Open up the FourFunctions.sv module you created in Exercise #1 by double-clicking it in the figure you just saw above. |
| - | - Create an empty file named **FourFunctions.sv** (note the extension ".sv" indicating a SystemVerilog file). This will be the text file that contains the SystemVerilog file for your lab. | + | - Start your file by creating a **header** in your SystemVerilog file that conforms to this class's [[:verilog_coding_standards]]. If Vivado has pre-populated the file with header information you are free to remove that or modify it (do not delete the first line that contains `timescale 1ns / 1ps, however. Either way, your design must have a **header** that conforms to the class's [[:verilog_coding_standards]] |
| - | - Start your file by creating a **header** in your SystemVerilog file that conforms to this class's [[:verilog_coding_standards]]. (NOTE: the coding standards are very specific on how to declare the inputs and outputs of modules. If you read carefully, you will note that they require the inclusion of the word "wire" in certain places. This is not reflected in the textbook examples. The need to include this is due to specific requirements of Vivado when the `default_nettype none macro directive is included.) | + | - NOTE: the coding standards are very specific on how to declare the inputs and outputs of modules. If you read carefully, you will note that they require the inclusion of the word "wire" in certain places. This is not reflected in the textbook examples. The need to include this is due to specific requirements of Vivado when the `default_nettype none macro directive is included.) |
| - | - Define a module named "FourFunctions" with the following ports. Make sure to match everything described below exactly (including the port names). | + | - Now, define a module named "FourFunctions" with the following ports. Make sure to match everything described below exactly (including the port names). |
| + | |||
| + | NOTE: if you are fuzzy on module declarations, consult the textbook. In particular, review Sections 8.3, 8.4, and 8.6.1 in the textbook. And, just remember that due to our using Vivado, you also need to include the word "wire" in certain places. Consult the [[:verilog_coding_standards]] for details on that. | ||
| + | |||
| + | Finaly, at this point remember there is no reason to get creative - just copy the structure and syntax (including indentation) of the code examples in the book sections noted. And, carefully follow the coding standard. This goes for this lab as well as all future labs. | ||
| **Module Name**: FourFunctions | **Module Name**: FourFunctions | ||
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| * **O4**: The logic function below: | * **O4**: The logic function below: | ||
| {{:labs:hwb.png?300|Function for O4}} | {{:labs:hwb.png?300|Function for O4}} | ||
| + | |||
| + | If these functions require intermediate signals (signals that are not module ports), you will need to declare them using the 'logic' keyword (see text for details). Also, choose meaninful names or (probably better yet) put a comment above them to tel what they are used for. | ||
| You do not need to minimize these functions, just implement the logic functions directly using basic gates (AND, NAND, OR, NOR, NOT, etc). | You do not need to minimize these functions, just implement the logic functions directly using basic gates (AND, NAND, OR, NOR, NOT, etc). | ||
| - | Complete your initial attempt at the SystemVerilog for these four functions before proceeding. In the next exercise you will have the opportunity to find and correct errors when you analyze the syntax and behavior of your SystemVerilog. | + | As you type and save your SystemVerilog code, Vivado will identify syntax errors in the code. Edit the code until there are no syntax errors. |
| - | + | ||
| - | **Exercise 1 Pass-off:** There is no pass off for this exercise.\\ \\ | + | |
| - | + | ||
| - | + | ||
| - | ==== Exercise #2: Creating a Vivado Project ==== | + | |
| - | + | ||
| - | Many software tools are needed to convert your SystemVerilog file into a configuration bit file that you can download onto an FPGA device. We will be using a set of tools called **Vivado** developed by Xilinx, the manufacturer of the FPGA devices in the lab. You will use Vivado throughout the rest of the semester. | + | |
| - | + | ||
| - | - Create a new Vivado project by following the instructions in the [[tutorials:vivado_project_setup]] tutorial. __Make sure you follow the steps in red to properly configure the error messages in your project.__ | + | |
| - | - Add the SystemVerilog file you created in exercise 1 to your project by following the [[tutorials:creating_a_new_module#adding_a_previously_created_module|adding a design file]] section of the Adding a SystemVerilog Module tutorial. | + | |
| - | * As you do so, create a NEW source file but don't set up any ports in the GUI at this time. | + | |
| - | * Then, copy and paste the SystemVerilog code you created earlier into this new design file. Make sure that the name you choose for the source file name matches the name of the module you have defined in your code. | + | |
| - | * Once you copy and paste the old code you no longer need that old file you created with the text editor and can delete it (recommended). | + | |
| - | * Any time you edit the code in your Vivado source file, the Vivado tools will perform basic syntax checking on the file. Any syntax errors will be highlighted and summarized in the messages tab. So, if the code you copied-and-pasted has syntax errors you will see them immediately. | + | |
| - | - Fix any syntax errors in your Vivado source code and then save. | + | |
| With no syntax errors in your HDL code you can perform **elaboration** and generate a notional schematic of the circuit. Follow the [[tutorials:viewing_design_elaboration]] tutorial to view a schematic of your code. | With no syntax errors in your HDL code you can perform **elaboration** and generate a notional schematic of the circuit. Follow the [[tutorials:viewing_design_elaboration]] tutorial to view a schematic of your code. | ||
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| Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | ||
| - | **Exercise 2 Pass-off:** Show a TA your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\ | + | **Exercise 2 Pass-off:** Review your code with a TA as well as your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions. |
| + | |||
| + | <color red> | ||
| + | Attach a screenshot of the resulting schematic to LearningSuite. | ||
| + | </color> | ||
| + | \\ \\ | ||
| - | /* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete. | ||
| - | */ | ||
| ==== Exercise #3: SystemVerilog Simulation ==== | ==== Exercise #3: SystemVerilog Simulation ==== | ||
| + | |||
| + | **If you are using Option #2: before beginning this step, you need to do the following just once to set up the tools:** | ||
| + | - Open a terminal in your Linux VM | ||
| + | - Type the following at a command prompt: sudo apt install gcc | ||
| + | - It will ask for your password | ||
| + | - It will install the needed C compiler for the simulator to work | ||
| + | |||
| + | **If you are running Option #1 or Option #3 you should not have to do the above step.** | ||
| Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. | ||
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| 3. Compare the resulting waveform with a truth table for your four functions. Verify that your simulation outputs match the expected outputs. If there are errors, fix your SystemVerilog file and simulate again until your circuit operates as intended. | 3. Compare the resulting waveform with a truth table for your four functions. Verify that your simulation outputs match the expected outputs. If there are errors, fix your SystemVerilog file and simulate again until your circuit operates as intended. | ||
| - | **Exercise 3 Pass-off:** Show a TA your simulation and explain how you know that your circuit is working correctly. The TA will also check your tcl commands to see if you have tested all possible input combinations.\\ \\ | + | 4. What if it doesn't simulate correctly? It could be that (a) your code is wrong of (b) there is something wrong with the simulation. Yes, we have found times when you can get the simulator in a weird state, where re-simulating doesn't seem to reflect your most recent code changes. On the wiki, there is a item on the left side near the top called "Taming Vivado". If the simulator is just not making sense you may need to follow the steps in "Taming Vivado" to fix it. You should learn how to do those steps so you are not totally stuck when you can't get help from a TA. |
| + | |||
| + | Go read through the "Taming Vivado" information right now. | ||
| + | |||
| + | <color red> | ||
| + | What are the steps, in order, to fix a "simulator-is-wedged" problem? | ||
| + | </color> | ||
| + | |||
| + | <color red> | ||
| + | Attach a PDF file of your Tcl file commands to LearningSuite. You can create such a PDF file from the File->Print menu in Vivado while editing it. | ||
| + | </color> | ||
| + | |||
| + | <color red> | ||
| + | Attach a screenshot of your simulation results that show how your circuit works as intended. In order to receive full credit on this (and all simulations for the rest of the semester), you MUST describe in detail in words in the LearningSuite response box for this question, how you went out verifying that it works. Point out the important time places in the simulation, what was happening there, what the inputs were, what the outputs were, and why they are the correct outputs, etc. | ||
| + | </color> | ||
| + | |||
| + | **Exercise 3 Pass-off:** Show a TA your simulation and explain it to him. The TA will also check your tcl commands to see if you have tested all possible input combinations.\\ \\ | ||
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| <color red>Indicate the number of **LUT**s (Look-up Tables) and **I/O** (Input/Output) pins for your design.</color> These are in the **Utilization** column of the table. | <color red>Indicate the number of **LUT**s (Look-up Tables) and **I/O** (Input/Output) pins for your design.</color> These are in the **Utilization** column of the table. | ||
| - | |||
| - | **Exercise 4 Pass-off:** No pass-off - just answer the questions above.\\ \\ | ||
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| Test all four functions in your circuit on the board to make sure that it works correctly. When you are convinced that your circuit is correct, proceed to the final pass off. | Test all four functions in your circuit on the board to make sure that it works correctly. When you are convinced that your circuit is correct, proceed to the final pass off. | ||
| - | <color red>Submit your final SystemVerilog code using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | <color red>Upload your FourFunctions SystemVerilog module. |
| + | The file(s) must be in PDF format. You can print to PDF directly from Vivado. | ||
| + | Then, attach it here to this question. | ||
| + | </color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Final Pass Off ===== | ===== Final Pass Off ===== | ||
| + | <color green> | ||
| + | Attach a video of your board (with narration) showing that your design is operating correctly. Be sure to show how all 4 functions are working correctly on the board. Your video must be right-side up, large enough to see, high enough quality to understand, and with sound that can be understood. | ||
| + | </color> | ||
| - | The following must be shown to a TA to pass off this laboratory: | + | =====Final Questions===== |
| - | * The circuit operating correctly on the FPGA board. | + | |
| <color red>How many hours did you work on the lab?</color> | <color red>How many hours did you work on the lab?</color> | ||
| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | |||
| + | /* | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
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| <color red>Describe your personal exploration activities</color> | <color red>Describe your personal exploration activities</color> | ||
| + | */ | ||
| /* | /* | ||
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| [[testDev]] | [[testDev]] | ||
| + | | ||
