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labs:sp20_stopwatch [2020/04/08 17:09] nelson [Exercise 3: Top-Level Module] |
labs:sp20_stopwatch [2020/05/19 17:08] (current) nelson [Exercise 3: Top-Level Module] |
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| ====== | ====== | ||
| - | ====== Stopwatch ====== | + | ====== Sp20 Stopwatch ====== |
| In this lab you will create a digital stopwatch. As shown in the video below, the stopwatch will be displayed on the eight-digit seven-segment display. | In this lab you will create a digital stopwatch. As shown in the video below, the stopwatch will be displayed on the eight-digit seven-segment display. | ||
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| * Connect your digit values output from the ''stopwatch'' module to the ''dataIn'' input of the ''SevenSegmentControl''. | * Connect your digit values output from the ''stopwatch'' module to the ''dataIn'' input of the ''SevenSegmentControl''. | ||
| * Turn on the appropriate decimal point. | * Turn on the appropriate decimal point. | ||
| - | * **Note:** The CPU_RESETN button is active-low. This means it behaves differently than the other buttons you have used: it is a ''0'' when pressed and a ''1'' otherwise. You will need to invert the signal when connecting it to your ''stopwatch'' and ''SevenSegmentControl'' modules. | + | * **Note:** The CPU_RESETN button is active-low. This means it behaves differently than the other buttons you have used: it is a ''0'' when pressed and a ''1'' otherwise. **You will need to invert the signal when connecting it to your ''stopwatch'' and ''SevenSegmentControl'' modules.** |
| Be sure to include an appropriate constraints file: | Be sure to include an appropriate constraints file: | ||
| Line 139: | Line 139: | ||
| **Exercise #3 Pass-off:** Nothing for this. | **Exercise #3 Pass-off:** Nothing for this. | ||
| + | |||
| + | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| =====Final Pass-Off===== | =====Final Pass-Off===== | ||
| - | Show the TAs your stopwatch working on the board. | + | <color green> |
| + | Attach a video (narrated) describing how your design operates. Time it to show that it really is counting seconds at the correct rate. Show how you can clear it at well and how you can start and stop it at will. Also, describe how long it will take for the counter to completely roll over and show that happening if it is feasible to do so. | ||
| + | </color> | ||
| - | <color red>Submit your SystemVerilog modules as part of the lab report on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| + | =====Final Questions===== | ||
| + | <color red> | ||
| + | How long (in hours) did you work on this lab? | ||
| + | </color> | ||
| - | =====Personal Exploration===== | + | <color red> |
| - | Here are some ideas for personal exploration in this laboratory: | + | List the pitfalls you encountered in this lab. What made it take longer than it should have (in your mind)? |
| - | * Use additional switches to make your stopwatch run faster or slower than real-time. | + | </color> |
| - | * Modify your design to work as a countdown timer when sw1 is high, and a count-up timer when sw0 is low. | + | |
