User Tools
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
labs:sp20_seven_segment [2020/04/08 16:49] nelson |
labs:sp20_seven_segment [2020/05/14 12:58] (current) nelson |
||
|---|---|---|---|
| Line 40: | Line 40: | ||
| Before you can create a circuit to display these hexadecimal characters, you need to determine the value each cathode signal needs for each character. | Before you can create a circuit to display these hexadecimal characters, you need to determine the value each cathode signal needs for each character. | ||
| - | <color red>Fill out the table below</color> so that the segment outputs on each row will display the number given by that row's hexadecimal character. Also included in this table is the binary representation of each hexadecimal character in the **D** columns. For an example, the output for an input of **0** is already in the table. | + | <color red>Fill out the table below</color> so that the segment outputs on each row will display the number given by that row's hexadecimal character. Also included in this table is the binary representation of each hexadecimal character in the **D** columns. For an example, the output for an input of **0** is already in the table. It was said already above but you probably missed it - you turn a segment ON by driving its cathode LOW. Carefully look at the top entry (for a '0') to make sure you understand this. |
| ^ Hex ^ Input ^^^^ Outputs ^^^^^^^ | ^ Hex ^ Input ^^^^ Outputs ^^^^^^^ | ||
| Line 144: | Line 144: | ||
| <color red>Copy and paste the testbench console output into your report (the console should report no errors).</color> | <color red>Copy and paste the testbench console output into your report (the console should report no errors).</color> | ||
| - | **Exercise 2 Pass-off:** Show a TA that your module passed the testbench without reporting any errors.\\ \\ | + | **Exercise 2 Pass-off:** Nothing to pass off, just be sure it is passing the testbench.\\ \\ |
| Line 222: | Line 222: | ||
| After completing your top-level design, simulate your top-level design to make sure your digit point (DP) logic and your anode logic is correct. Also, simulate all possible data inputs to verify your top-level circuit is working properly. | After completing your top-level design, simulate your top-level design to make sure your digit point (DP) logic and your anode logic is correct. Also, simulate all possible data inputs to verify your top-level circuit is working properly. | ||
| + | <color red> | ||
| + | Attach your top-level module to LearningSuite. | ||
| + | </color> | ||
| - | **Exercise 3 Pass-off:** Show a TA your code for the top-level module and your working simulation.\\ \\ | + | <color red> |
| + | Attach a screenshot of your working simulation to LearningSuite. | ||
| + | </color> | ||
| + | |||
| + | **Exercise 3 Pass-off:** Nothing to pass off - just answer the questions above.\\ \\ | ||
| Line 244: | Line 251: | ||
| [[tutorials:bitgen|Generate a bitfile]] for your design, download your circuit, and verify that it works as expected. | [[tutorials:bitgen|Generate a bitfile]] for your design, download your circuit, and verify that it works as expected. | ||
| - | ===== Final Pass Off ===== | + | ====Final Pass-Off:==== |
| + | <color green>Attach a video (narrated) showing your circuit working correctly on the board. Show that it displays what it ought to as you manipulate the switches and btnc.</color> | ||
| - | Show the following to a TA to pass off your lab: | + | <color green>Explain why we aren't able to display two different numbers on two different digits at the same time.</color> |
| - | * Pass offs for Exercises 1, 2, and 3. | + | |
| - | * Your circuit operating correctly on the FPGA board. | + | |
| - | * Explain why we aren't able to display two different numbers on two different digits at the same time. | + | |
| <color red>How many hours did you work on the lab?</color> | <color red>How many hours did you work on the lab?</color> | ||
| Line 271: | Line 276: | ||
| */ | */ | ||
| + | /* Listing of errors helped with: | ||
| + | - One student made his .tcl simulation file as a constraints file (had a .tcl extension but was in the Design Sources pane). Synthesis didn't like that... | ||
| + | |||
| + | */ | ||
| ---- | ---- | ||
| [[labs:ta:seven_segment_decoder|TA Notes and Feedback]] | [[labs:ta:seven_segment_decoder|TA Notes and Feedback]] | ||
