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labs:sp20_intro_digital_systems [2020/04/30 11:34] nelson [Exercise #1 - Introduction to the BYU Digital lab] |
labs:sp20_intro_digital_systems [2020/05/04 11:38] (current) nelson [Final Questions.] |
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It is a good idea to make an **ECEn220** folder in your J Drive, make a **labs** folder inside of that. You should also create a sub-directory for each lab in the course. You will be generating a lot of files for these labs and need to keep them separate. | It is a good idea to make an **ECEn220** folder in your J Drive, make a **labs** folder inside of that. You should also create a sub-directory for each lab in the course. You will be generating a lot of files for these labs and need to keep them separate. | ||
- | ===What is the Red Text?=== | ||
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- | So, why is the text below in <color red>red</color>? You will be completing a lab writeup on Learning Suite. Things in the labs are marked red to signal to you that those things are some of what will be asked for as you complete the lab writeup. As you run across them, you should write the questions and answers in your lab notebook so when you go to complete the lab writeup you will have the information you need. | ||
<color red>Indicate your CAEDM user ID.</color>\\ | <color red>Indicate your CAEDM user ID.</color>\\ | ||
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In this next exercise, you will configure the FPGA with a different circuit. To use and experiment with this new circuit, you need to load {{ :labs:nexys4byuuserdemo.bit |this configuration, or bit, file}} onto the FPGA. You will be loading bit files on the the FPGA for **every** lab each week. You will be creating your own bit files in future lab assignments from the circuits you design. | In this next exercise, you will configure the FPGA with a different circuit. To use and experiment with this new circuit, you need to load {{ :labs:nexys4byuuserdemo.bit |this configuration, or bit, file}} onto the FPGA. You will be loading bit files on the the FPGA for **every** lab each week. You will be creating your own bit files in future lab assignments from the circuits you design. | ||
- | Follow [[tutorials:downloading_bitfile|this tutorial]] to program the FPGA with the new bit file! | + | In this case, download the above bitfile onto your computer using whatever mechanism your browser supports. |
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+ | Then, if you are using **Option #1** or **Options #2**, follow [[tutorials:downloading_bitfile|this tutorial]] (top part) to program the FPGA with the new bit file using Xilinx tools. | ||
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+ | But, if you are using **Option #3** you will run Adept and select the bitfile to program onto your board. Ask a TA if you need help with Adept. | ||
The FPGA should now be acting differently in its behavior than when you first powered it on. | The FPGA should now be acting differently in its behavior than when you first powered it on. | ||
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- After five seconds of recording, the circuit will then play back the audio. This playback is indicated by the LEDs turning on from right to left. | - After five seconds of recording, the circuit will then play back the audio. This playback is indicated by the LEDs turning on from right to left. | ||
- | <color red> Based on what you heard, is it a high or low quality microphone?</color> | + | <color red> Based on what you heard, what can you say about the microphone and speaker setup: is it high or low quality, is it stereo or mono?</color> |
=====Final Pass-Off===== | =====Final Pass-Off===== | ||
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Answer the following questions: | Answer the following questions: | ||
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+ | <color red>Describe your final machine setup so we can make sure the most knowledgeable TA corrects your work. Is it Windows or a Mac? Are you doing Option #1, #2, or #3? </color> | ||
<color red>How many hours did you work on the lab?</color> | <color red>How many hours did you work on the lab?</color> |