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labs:sp20_debounce [2020/04/28 17:07] nelson [Personal Exploration] |
labs:sp20_debounce [2020/05/28 18:42] (current) nelson [Debounce State Machine] |
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| - | ====== Debounce State Machine ====== | + | ====== Sp20 Debounce State Machine ====== |
| You will create a debounce state machine and use this state machine to debounce the button on the NEXYS4 board to reliably count the number of times the button is pressed. | You will create a debounce state machine and use this state machine to debounce the button on the NEXYS4 board to reliably count the number of times the button is pressed. | ||
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| Carefully read and review Chapter 26 of the textbook. This lab will closely follow that design. | Carefully read and review Chapter 26 of the textbook. This lab will closely follow that design. | ||
| - | Figure 26.1 in the textbook demonstrates the "noise" that occurs with mechanical buttons or switches. In this figure, the button signal starts at zero, transitions between zero and one, and then settles down to one. | + | Figure 26.1 in the textbook demonstrates the "noise" that occurs with mechanical buttons or switches. In this figure, the button signal starts at zero, transitions between zero and one, and then settles down to one. But, the same noise can happen when the button signal later transitions from one to zero. |
| <color red>Assuming a 100 MHz clock (10 ns period), how many clock cycles are needed to implement a delay of at least 5 ms?</color> | <color red>Assuming a 100 MHz clock (10 ns period), how many clock cycles are needed to implement a delay of at least 5 ms?</color> | ||
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| Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | ||
| */ | */ | ||
| - | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone". Your counter should be cleared when clrTimer is asserted by the state machine. | + | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone". Your counter should be cleared when clrTimer is asserted by the state machine. You DO NOT wire the reset signal for your overall circuit to the clr on the timer. Rather, the state machine is in charge here - your state machine design will reset the timer when it needs to. |
| By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | ||
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| {{ :labs:tb_debounce.v |}} | {{ :labs:tb_debounce.v |}} | ||
| - | <color red>Include a copy of your testbench output in your lab report</color> | + | <color red>Include a copy of your testbench output that shows you had 0 errors.</color> |
| **Exercise 2 Pass-off:** No passoff, just make sure that you passed the testbench with zero errors.\\ \\ | **Exercise 2 Pass-off:** No passoff, just make sure that you passed the testbench with zero errors.\\ \\ | ||
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| After completing your top-level module, create a TCL script to simulate at least three "noisy" button presses on your top-level design. Verify that your design counts properly in these noisy button press situations. | After completing your top-level module, create a TCL script to simulate at least three "noisy" button presses on your top-level design. Verify that your design counts properly in these noisy button press situations. | ||
| - | <color red>Attach your code and your Tcl script to the Lab Writeup page (there are locations to do so). Your simulation must show the expected behavior of your debounce module. | + | <color red>Attach your Tcl script to the Lab Writeup page. Your simulation must show the expected behavior of your debounce module. |
| </color> | </color> | ||
| + | |||
| + | <color red>Attach PDF of your **debounce** SystemVerilog module. </color> | ||
| + | |||
| + | <color red>Attach PDF of your **debounce_top** SystemVerilog module. </color> | ||
| **Exercise #3 Pass-Off:** Nothing to be passed off in person. \\ \\ | **Exercise #3 Pass-Off:** Nothing to be passed off in person. \\ \\ | ||
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| /* TODO: have them do a timing analysis on the circuit - this is the first fully synchronouos design */ | /* TODO: have them do a timing analysis on the circuit - this is the first fully synchronouos design */ | ||
| - | Once the bitstream has been generated, download your bitstream to verify that it works correctly. After downloading your circuit, press the button several times to see if you can see a difference between the counter using the debounce state machine and the counter that does not use the debug state machine. | + | Once the bitstream has been generated, download your bitstream to verify that it works correctly. After downloading your circuit, press the button several times to see if you can see a difference between the counter using the debounce state machine and the counter that does not use the debug state machine. What you see will depend on just how "bouncy" your button is. It may bounce almost every time you push it or it may rarely bounce. |
| <color red>Summarize the results from your experiments comparing the debounced counter value to the non-debounced counter value.</color> | <color red>Summarize the results from your experiments comparing the debounced counter value to the non-debounced counter value.</color> | ||
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| ===== Final Pass Off ===== | ===== Final Pass Off ===== | ||
| <color green> | <color green> | ||
| - | Demonstrate your circuit operating on the FPGA board to the TA. Carefully read through the entire lab and then describe and demonstrates how it meets all requirements you were given. | + | Attach a link to a video demonstrating your circuit operating on the FPGA board. Carefully read through the entire lab and then describe and demonstrates how it meets all requirements you were given. |
| - | </color> | + | Be sure to include a demonstration of your characterizing just how bouncy your button is in terms of the % of button pushes that bounce. |
| - | + | ||
| - | <color green> | + | |
| - | Characterize just how bouncy your button is in terms of the % of button pushes that bounce. Use a large enough trials to make your analysis meaningful. Also, create a histogram on paper and show in your video how often, when it bounces, it bounces just twice, three times, etc. What is the largest number of bounces? What is the average? What is the median? | + | |
| </color> | </color> | ||
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| <color red>Please provide any suggestions for improving this lab in the future.</color> | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| - | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | + | /*<color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). */ |
| [[labs:ta:debounce|TA Notes and Feedback]] | [[labs:ta:debounce|TA Notes and Feedback]] | ||
