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labs:sp20_arithmetic [2020/05/11 13:17] 127.0.0.1 external edit |
labs:sp20_arithmetic [2020/05/14 13:08] (current) nelson |
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| Line 18: | Line 18: | ||
| * 10000100 | * 10000100 | ||
| * 00011001 | * 00011001 | ||
| - | * 01100111 | + | |
| - | * 10100100 | + | |
| <color red> | <color red> | ||
| Extend each of the following numbers to nine bits using //sign-extension//: | Extend each of the following numbers to nine bits using //sign-extension//: | ||
| Line 26: | Line 24: | ||
| * 10000100 | * 10000100 | ||
| * 00011001 | * 00011001 | ||
| - | * 01100111 | + | |
| - | * 10100100 | + | |
| <color red> | <color red> | ||
| Negate each of the two's complement numbers from the previous question. | Negate each of the two's complement numbers from the previous question. | ||
| Line 44: | Line 40: | ||
| 2) 001100100 | 2) 001100100 | ||
| + 000011001 | + 000011001 | ||
| - | |||
| - | 3) 001100111 | ||
| - | + 000100100 | ||
| - | |||
| - | 4) 001100111 | ||
| - | + 110100100 | ||
| </code> | </code> | ||
| Line 62: | Line 52: | ||
| 2) 001100100 | 2) 001100100 | ||
| - 000011001 | - 000011001 | ||
| - | |||
| - | 3) 001100111 | ||
| - | - 000100100 | ||
| - | |||
| - | 4) 001100111 | ||
| - | - 110100100 | ||
| </code> | </code> | ||
| Line 185: | Line 169: | ||
| | sw | Input | 16 | Switches (sw[15:8] = A input, sw[7:0] = B) | | | sw | Input | 16 | Switches (sw[15:8] = A input, sw[7:0] = B) | | ||
| | led | Output | 9 | LED signals (result) | | | led | Output | 9 | LED signals (result) | | ||
| + | |||
| + | **NOTE: the name of the module and of the ports are crucial - use what is in the table above. | ||
| + | The reason is that the testbench you will use below to prove your circuit works will rely on it being called 'arithmetic_top' and on the ports | ||
| + | having the names above. | ||
| + | And, just for uniformity sakes, call your file 'arithmetic_top.sv' - the convention is typically to have them be the same to minimize confusion.** | ||
| A block diagram of the overall design is shown below. | A block diagram of the overall design is shown below. | ||
| - | {{:labs:lab_4:lab4Top.png?6700|}} | + | {{:labs:lab_4:lab4top.png?6700|}} |
| This is different from how we did things in the last lab, why? If you recall, in the last lab you took a copy of the master .xdc file for the board, uncommented out the switches and lights you wanted to use and then changed the names of the signals mapped to those switches and lights so it would match your design (A, B, C, O1, O2, ...). This week's lab represents an alternate approach. Here, your top level SystemVerilog module will have names that match what is in the .xdc file and so all you have to do is uncomment the appropriate lines in the .xdc file. | This is different from how we did things in the last lab, why? If you recall, in the last lab you took a copy of the master .xdc file for the board, uncommented out the switches and lights you wanted to use and then changed the names of the signals mapped to those switches and lights so it would match your design (A, B, C, O1, O2, ...). This week's lab represents an alternate approach. Here, your top level SystemVerilog module will have names that match what is in the .xdc file and so all you have to do is uncomment the appropriate lines in the .xdc file. | ||
| Line 198: | Line 187: | ||
| How should you do that? There are two ways: (1) you could figure out how to sign extend as an expression that you pass to the Add9 instance you create or | How should you do that? There are two ways: (1) you could figure out how to sign extend as an expression that you pass to the Add9 instance you create or | ||
| (2) you could declare two new signals that are 9 bits wide, use 'assign' statements to sign extend your two inputs to those signals, | (2) you could declare two new signals that are 9 bits wide, use 'assign' statements to sign extend your two inputs to those signals, | ||
| - | and then wire those new signals up to your Add9 module. | + | and then wire those new signals up to your Add9 module. Either way, you do not create a 'Sign extend' module - it is just some logic in your top module. |
| - | It is your choice of how to do it. | + | |
| Also, the carry out of your adder is not used, but you do need to connect something to it. So, declare a wire in your top-level module and attach it to the carry out of your adder. | Also, the carry out of your adder is not used, but you do need to connect something to it. So, declare a wire in your top-level module and attach it to the carry out of your adder. | ||
| But, do not connect it to anything else - the synthesis tool will recognize that it is unused and throw it away. | But, do not connect it to anything else - the synthesis tool will recognize that it is unused and throw it away. | ||
| + | |||
| Similarly, the carry in of your adder needs to be tied to a '0' value. You have two ways of doing this. | Similarly, the carry in of your adder needs to be tied to a '0' value. You have two ways of doing this. | ||
| - | The first is to simple tie a 1'b0 as the carry in to your Add9 module. The second is to declare a wire for this purpose | + | The first is to simply tie a 1'b0 as the carry in to your Add9 module when you instance it in 'arithmetic_top'. The second is to declare a wire for this purpose |
| - | and use an 'assign' statement to assign it to a constant '0' | + | and use an 'assign' statement to assign it to a constant '0' and then wire that signal into 'arithmetic_top'. |
| - | value. It is your choice of how to do this. | + | It is your choice of how to do this. |
| === Simulating with a Testbench === | === Simulating with a Testbench === | ||
| Line 216: | Line 205: | ||
| When you have completed your top-level design and removed all syntax errors, simulate your design manually to convince yourself that your circuit is working properly. Once you believe your circuit is working properly, download the following {{ :labs:tb_arithmetic.sv }} file and simulate your module with this testbench. Read through the [[tutorials:testbench_tutorial|testbench tutorial]] to learn how to add and use a testbench for your verification. The testbench will run automatically, but you might need additional run time for it to finish. To do this, simply type a "run all" command into the TCL command line. The simulation will stop when the testbench ends. | When you have completed your top-level design and removed all syntax errors, simulate your design manually to convince yourself that your circuit is working properly. Once you believe your circuit is working properly, download the following {{ :labs:tb_arithmetic.sv }} file and simulate your module with this testbench. Read through the [[tutorials:testbench_tutorial|testbench tutorial]] to learn how to add and use a testbench for your verification. The testbench will run automatically, but you might need additional run time for it to finish. To do this, simply type a "run all" command into the TCL command line. The simulation will stop when the testbench ends. | ||
| - | The testbench will simulate your circuit's four different modes of operation to make sure that the output of your circuit is correct for each case. The testbench will continue until it prints out a **Simulation done** message indicating the number of errors that were found. Make sure you have 0 errors before proceeding to the next exercise. | + | The testbench will simulate your circuit's operation to make sure that the output of your circuit is correct for each case. |
| + | The testbench will continue until it prints out a **Simulation done** message indicating the number of errors that were found. Make sure you have 0 | ||
| + | errors before proceeding to the next exercise. | ||
| **What to do if it doesn't work? How do I debug it?** | **What to do if it doesn't work? How do I debug it?** | ||
| Line 254: | Line 244: | ||
| ===== Final Passoff ===== | ===== Final Passoff ===== | ||
| <color green> | <color green> | ||
| - | Attach a video (narrated) of circuit working on the Nexys4 board for final passoff. Show that it works for a variety of values. | + | Attach the link to a video (preferred) at some site like Youtube, Dropbox, etc. of your circuit working on the Nexys4 board for final passoff. Alternatively, attach the video itself if it will fit. |
| - | Show that all the bit positions work (don't just choose small numbers to add). | + | </color> |
| - | For the 4 cases below, do the addition with multiple pairs of numbers for each case: | + | |
| + | <color green> | ||
| + | There are now some additions to the [[:verilog_coding_standards|Verilog Coding Standards]] regarding how to attach a video. Please follow them as you attach. | ||
| + | </color> | ||
| + | |||
| + | <color green> | ||
| + | Show that it works for a variety of values. Show that all the bit positions work (don't just choose small numbers to add). For the 4 cases below, do the addition with multiple pairs of numbers for each case: | ||
| </color> | </color> | ||
| Line 310: | Line 306: | ||
| ---- | ---- | ||
| + | /* Problems helped with: | ||
| + | - Top level had pin (cout) which was not mapped to a board level port. | ||
| + | - Should have made it a local signal. | ||
| + | */ | ||
| [[labs:ta:arithmetic|TA Notes and Feedback]] | [[labs:ta:arithmetic|TA Notes and Feedback]] | ||
