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--- labs:sp20_arithmetic [2020/05/11 12:16]
127.0.0.1 external edit
+++ labs:sp20_arithmetic [2020/05/14 13:08] (current)
nelson
@@ Line 18: / Line 18: @@
   * 10000100
   * 00011001
-  * 01100111
-  * 10100100
 <color red>
 Extend each of the following numbers to nine bits using //sign-extension//:
@@ Line 26: / Line 24: @@
   * 10000100
   * 00011001
-  * 01100111
-  * 10100100
 <color red>
 Negate each of the  two's complement numbers from the previous question.
@@ Line 44: / Line 40: @@
 )   001100100
    + 000011001
-)   001100111
-   + 000100100
-)   001100111
-   + 110100100
 </code>
@@ Line 62: / Line 52: @@
 )   001100100
    - 000011001
-)   001100111
-   - 000100100
-)   001100111
-   - 110100100
 </code>
@@ Line 186: / Line 170: @@
 | led | Output | 9 | LED signals (result)  |
-This is not a very interesting top level module --- all it does is it instances a copy of your adder and connects the adder's inputs and outputs to the board's switches and lights.  Why would even do it this way, then?
+**NOTE: the name of the module and of the ports are crucial - use what is in the table above.
+The reason is that the testbench you will use below to prove your circuit works will rely on it being called 'arithmetic_top' and on the ports
-If you recall, in the last lab you took a copy of the master .xdc file for the board, uncommented out the switches and lights you wanted to use and then changed the names of the signals mapped to those switches and lights so it would match your design (O1, O2, ...).  This week's lab represents an alternate approach.  Here, your top level SystemVerilog module will have names that match what is in the .xdc file and so all you have to do is uncomment the appropriate lines in the .xdc file.
+having the names above.
+And, just for uniformity sakes, call your file 'arithmetic_top.sv' - the convention is typically to have them be the same to minimize confusion.**
-This has the advantage that your SystemVerilog code uses names like 'sw' and 'led' for the signal names, making it clear during the design and simulation stage just what signal is connected where to the board.
-Importantly, it also has the benefit that you can put additional logic into this top level module.  For example, what if you wanted to have some of the buttons control how your adder works (cause it to add or subtract like the circuit of Figure 9.4)?   You could put the additional logic into the top level module.
-Before instancing your Add9.sv module, you will need to create the logic for its **a** and **b** inputs to your module. The descriptions below will guide you through the process of designing this logic. After you create this logic, you will then instance your Add9.sv module.
 A block diagram of the overall design is shown below.
-/*{{:labs:lab_4:img_0072.jpg?6700|}}*/
+{{:labs:lab_4:lab4top.png?6700|}}
-{{:labs:lab_4:lab4Top.png?6700|}}
-A description of the additional logic you are to implement is as follows.  But, first, note that you //do not// need to create a new module declaration for the block marked "Logic" in the above diagram.  It is just drawn that way to encapsulate all the logic you are going to need to create.
-  * Switches sw[15:8] from the nexys4 board are interpreted as a twos-complement number and will be used as the **left** operand for addition/subtraction.
-  * Switches sw[7:0] are also interpreted as a two's-complement number and will be used as the **right** operand for addition/subtraction.
-  * The a and b inputs to your Add9.sv module are nine bits.  But, you only have 8 bit inputs fromthe switches.  You will need to sign extend both of the 8-bit inputs from the switches into 9-bit value for use by your Add9.sv module. Do you remember how to sign-extend a 2's complement number?  In SystemVerilog you can use an //assign// statement to concat some of the original 8 bits into a 9 bit quantity and assign it to a new local signal you have declared with the //logic// keyword.
-  * Under normal conditions (no buttons pressed), the two operands will be added together.
-  * When the right button (**btnr**) is pressed, you will need to perform a two's complement negation (see 3.3.2 of the book) of the **right** operand, which will cause the adder to compute **left + -right**.
-  * When the left button (**btnl**) is pressed, you need to zero out the **left** operand. Once again, this will require that you declare a new local signal using the //logic// keyword and use an //assign// statement to do the zeroing out.  These two functions will be described in more detail below.
-=== Subtraction ===
-You must design your circuit so that you can perform **subtraction**, **left** minus **right**, when the right button is pressed. To perform subtraction, you simply need to perform a two's complement negation of the **right** operand. This involves two steps as described in section 9.2 of the textbook:
-  - Each bit of the **right** operand is XOR'd with the **btnr** signal before being connected to the Full Adder
-  - The carry-in of the first stage of the Full Adder should be set to a '1' when **btnr** is pressed (and '0' otherwise)
-Your circuit will look much like Figure 9.4 in the text with the difference being that Figure 9.4 uses an inverted **addSub#** signal which subtracts when it is '0', while your circuit uses the **btnr** signal which subtracts when it is '1'.
-You can implement this conditional inverting and forcing the cin to a '1' using a couple of //assign// statements to and some local signals declared using the //logic// keyword.
-/* have them add an exercise to understand how this circuit works?
-^ btnr ^ B ^ XOR ^
-| 0 | 0 | 0 (B) |
-| 0 | 1 | 1 (B) |
-| 1 | 0 | 1 (~B) |
-| 1 | 1 | 0 (~B) |
-*/
-=== Zeroing The **left** Operand ===
-In addition to subtraction, you must design your circuit so that you can zero the **left** operand when the left button (**btnl**) is pressed. Do this by ANDing each bit of the **left** operand with **~btnl** and connecting the result to your Add9 module. This way, when **btnl** = 0 the value of A will be passed to the Full Adder and when **btnl** = 1 nine zeroes will get passed instead.  Use an //assign// statement and local signal for this.
-With the two buttons your top-level circuit should implement the following four functions:
-^ btnr ^ btnl ^ Function ^
-| 0 | 0 | Addition (left+right) |
-| 0 | 1 | Pass right (0+right) |
-| 1 | 0 | Subtraction (left-right) |
-| 1 | 1 | Pass -right (0-right) |
-=== Putting it all together ===
-Now, instance your Add9.sv module into the top-level design.
+This is different from how we did things in the last lab, why?  If you recall, in the last lab you took a copy of the master .xdc file for the board, uncommented out the switches and lights you wanted to use and then changed the names of the signals mapped to those switches and lights so it would match your design (A, B, C, O1, O2, ...).  This week's lab represents an alternate approach.  Here, your top level SystemVerilog module will have names that match what is in the .xdc file and so all you have to do is uncomment the appropriate lines in the .xdc file.
-The 'sum' output of your Add9.sv module should be attached directly to the 'led' outputs of your top-level circuit (this way, your result will visible on nine of the Nexys4 LEDs).
+This has the advantage that your SystemVerilog code uses names like 'sw' and 'led' for the signal names, making it clear during the design and simulation stage just what signal is connected where to the board.
-The carry out of your adder is not used but you do need to connect something to it. So, declare a wire in your top-level module and attach it to the carry out of your adder. But, do not connect it to anything else - the synthesis tool will recognize that it is unused and throw it away.
+Importantly, it also has the benefit that you can put additional logic into this top level module.
+In this case you will put logic into the top level module to do the sign extension of your two inputs.
+How should you do that?  There are two ways: (1) you could figure out how to sign extend as an expression that you pass to the Add9 instance you create or
+(2) you could declare two new signals that are 9 bits wide, use 'assign' statements to sign extend your two inputs to those signals,
+and then wire those new signals up to your Add9 module.  Either way, you do not create a 'Sign extend' module - it is just some logic in your top module.
-In total, your top module should include:
+Also, the carry out of your adder is not used, but you do need to connect something to it. So, declare a wire in your top-level module and attach it to the carry out of your adder.
-  - Logic for zeroing the left operand
+But, do not connect it to anything else - the synthesis tool will recognize that it is unused and throw it away.
-  - Logic for negating the right operand
-  - An instance of your nine-bit adder correctly connected to the previous logic elements and to the LEDs as outputs.
+Similarly, the carry in of your adder needs to be tied to a '0' value.  You have two ways of doing this.
+The first is to simply tie a 1'b0 as the carry in to your Add9 module when you instance it in 'arithmetic_top'.  The second is to declare a wire for this purpose
+and use an 'assign' statement to assign it to a constant '0' and then wire that signal into 'arithmetic_top'.
+It is your choice of how to do this.
 === Simulating with a Testbench ===
@@ Line 262: / Line 203: @@
 Digital circuits are often tested with special SystemVerilog modules called **testbenches**. Testbenches are SystemVerilog files that are used to //test// your circuit and are not used for designing new logic circuts. Testbenches are written differently than synthesizable SystemVerilog and are used to provide more thorough testing of digital circuits than is possible with TCL files. In this lab, and all future labs, you will be given a SystemVerilog testbench file that will test your circuit.
-When you have completed your top-level design and removed all syntax errors, simulate your design manually to convince yourself that your circuit is working properly. Once you believe your circuit is working properly, download the following {{ :labs:tb_arithmetic.v }} file and simulate your module with this testbench. Read through the [[tutorials:testbench_tutorial|testbench tutorial]] to learn how to add and use a testbench for your verification. The testbench will run automatically, but you might need additional run time for it to finish. To do this, simply type a "run all" command into the TCL command line. The simulation will stop when the testbench ends.
+When you have completed your top-level design and removed all syntax errors, simulate your design manually to convince yourself that your circuit is working properly. Once you believe your circuit is working properly, download the following {{ :labs:tb_arithmetic.sv }} file and simulate your module with this testbench. Read through the [[tutorials:testbench_tutorial|testbench tutorial]] to learn how to add and use a testbench for your verification. The testbench will run automatically, but you might need additional run time for it to finish. To do this, simply type a "run all" command into the TCL command line. The simulation will stop when the testbench ends.
-The testbench will simulate your circuit's four different modes of operation to make sure that the output of your circuit is correct for each case. The testbench will continue until it prints out a **Simulation done** message indicating the number of errors that were found. Make sure you have 0 errors before proceeding to the next exercise.
+The testbench will simulate your circuit's operation to make sure that the output of your circuit is correct for each case.
+The testbench will continue until it prints out a **Simulation done** message indicating the number of errors that were found. Make sure you have 0
+errors before proceeding to the next exercise.
 **What to do if it doesn't work?  How do I debug it?**
@@ Line 283: / Line 225: @@
 ==== Exercise #3 - Synthesize, Implement and Download ====
-For this final exercise, you can proceed with the implementation and downloading of your design. Begin this process by [[tutorials:making_an_xdc_file|creating]] and [[tutorials:adding_an_xdc_file|adding]] an XDC constraints file. Your file should have entries for all 16 switches, two button inputs (**btnr** and **btnl**) and 9 led outputs. The easiest way to create this file is to start with the {{ :resources:nexys4_220.xdc|master .xdc}} file and modify it with the signals you will use by uncommenting the ports you use and making sure the port names and your top-level signal names match.
+For this final exercise, you can proceed with the implementation and downloading of your design. Begin this process by [[tutorials:making_an_xdc_file|creating]] and [[tutorials:adding_an_xdc_file|adding]] an XDC constraints file. Your file should have entries for all 16 switches and 9 led outputs.
+The easiest way to create this file is to start with the {{ :resources:nexys4_220.xdc|master .xdc}} file and modify it with the signals you will use by uncommenting the ports
+you use and making sure the port names and your top-level signal names match (they should if you followed the instructions above).
 Once you have added the XDC file to your project, [[tutorials:synthesis|synthesize]] your project.
@@ Line 300: / Line 244: @@
 ===== Final Passoff =====
 <color green>
-Attach a video (narrated) of circuit working on the Nexys4 board for final passoff. Show that it works for a variety of values.
+Attach the link to a video (preferred) at some site like Youtube, Dropbox, etc. of your circuit working on the Nexys4 board for final passoff. Alternatively, attach the video itself if it will fit.
-Show that all the bit positions work (don't just choose small numbers to add).
+</color>
-For the 4 cases below, do the addition with multiple pairs of numbers for each case:
+<color green>
+There are now some additions to the [[:verilog_coding_standards|Verilog Coding Standards]] regarding how to attach a video.  Please follow them as you attach.
+</color>
+<color green>
+Show that it works for a variety of values. Show that all the bit positions work (don't just choose small numbers to add). For the 4 cases below, do the addition with multiple pairs of numbers for each case:
 </color>
@@ Line 356: / Line 306: @@
 ----
+/* Problems helped with:
+  - Top level had pin (cout) which was not mapped to a board level port.
+  - Should have made it a local signal.
+*/
 [[labs:ta:arithmetic|TA Notes and Feedback]]

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