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labs:seven_segment_controller [2019/05/30 12:58] jgoeders [Exercise #3 - Top-Level Circuit] |
labs:seven_segment_controller [2019/05/30 12:59] (current) jgoeders [Exercise #3 - Top-Level Circuit] |
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| | anode | Output | 8 | Anode signals for each of the eight digits | | | anode | Output | 8 | Anode signals for each of the eight digits | | ||
| - | Begin the body of your module by instancing your seven segment controller and attaching the clk input to the top-level clock and the segment and anode signals to the top-level segment and anode signals. You will need to create additional logic to control the other signals of your seven segment controller (dataIn, digitDisplay, and digitPoint). In particular, your logic will generate the values for these signals based on the values of the top-level buttons and switches. The figure below provides a high-level diagram of how you should organize your top-level design. | + | Begin the body of your module by instancing your seven segment controller and attaching the ''clk'' input to the top-level clock, the ''CPU_RESETN'' to the ''reset'' input (remember to invert it), and the ''segment'' and ''anode'' signals to the top-level ''segment'' and ''anode'' signals. You will need to create additional logic to control the other signals of your seven segment controller (dataIn, digitDisplay, and digitPoint). In particular, your logic will generate the values for these signals based on the values of the top-level buttons and switches. The figure below provides a high-level diagram of how you should organize your top-level design. |
| {{ :labs:seven_segment_control_top.png?nolink&500 |}} | {{ :labs:seven_segment_control_top.png?nolink&500 |}} | ||
