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labs:seven_segment_controller [2018/10/31 13:16] kenmcg [Exercise #3 - Top-Level Circuit] |
labs:seven_segment_controller [2019/05/30 12:59] (current) jgoeders [Exercise #3 - Top-Level Circuit] |
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
| + | | reset | Input | 1 | Active high reset, which resets the counter | | ||
| | dataIn | Input | 32 | Data value to display | | | dataIn | Input | 32 | Data value to display | | ||
| | digitDisplay | Input | 8 | Indicates which digits to display | | | digitDisplay | Input | 8 | Indicates which digits to display | | ||
| Line 132: | Line 133: | ||
| Finally, you will need an 8:1 multiplexer for the digit point cathode logic. | Finally, you will need an 8:1 multiplexer for the digit point cathode logic. | ||
| + | |||
| + | ** Exercise 1 Pass-off:** Show a TA your completed module and briefly explain how your anode and cathode sections work.\\ \\ | ||
| + | |||
| ==== Exercise #2 - Seven Segment Controller Verification ==== | ==== Exercise #2 - Seven Segment Controller Verification ==== | ||
| Line 144: | Line 148: | ||
| <code> | <code> | ||
| + | restart | ||
| + | |||
| # Set a repeating clock | # Set a repeating clock | ||
| add_force clk {0 0} {1 5} -repeat_every 10 | add_force clk {0 0} {1 5} -repeat_every 10 | ||
| + | add_force reset 1 | ||
| + | run 20ns | ||
| + | add_force reset 0 | ||
| # set default values for the inputs | # set default values for the inputs | ||
| add_force -radix hex dataIn 01234567 | add_force -radix hex dataIn 01234567 | ||
| Line 175: | Line 184: | ||
| {{ :labs:tb_sevensegmentcontrol.v |}} | {{ :labs:tb_sevensegmentcontrol.v |}} | ||
| - | |||
| - | <color red>Include the console output of your correctly operating controller running the testbench</color> | ||
| <color red>Include a copy of your seven segment controller SystemVerilog</color> | <color red>Include a copy of your seven segment controller SystemVerilog</color> | ||
| + | ** Exercise 2 Pass-off:** Show a TA your extended tcl script and your testbench output.\\ \\ | ||
| ==== Exercise #3 - Top-Level Circuit ==== | ==== Exercise #3 - Top-Level Circuit ==== | ||
| Line 188: | Line 196: | ||
| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
| + | | CPU_RESETN | Input | 1 | Active-low reset button | | ||
| | sw | Input | 16 | 16 Slide switches to determine what to display | | | sw | Input | 16 | 16 Slide switches to determine what to display | | ||
| | btnc | Input | 1 | Assert all segments (test mode) | | | btnc | Input | 1 | Assert all segments (test mode) | | ||
| Line 201: | Line 210: | ||
| | anode | Output | 8 | Anode signals for each of the eight digits | | | anode | Output | 8 | Anode signals for each of the eight digits | | ||
| - | Begin the body of your module by instancing your seven segment controller and attaching the clk input to the top-level clock and the segment and anode signals to the top-level segment and anode signals. You will need to create additional logic to control the other signals of your seven segment controller (dataIn, digitDisplay, and digitPoint). In particular, your logic will generate the values for these signals based on the values of the top-level buttons and switches. The figure below provides a high-level diagram of how you should organize your top-level design. | + | Begin the body of your module by instancing your seven segment controller and attaching the ''clk'' input to the top-level clock, the ''CPU_RESETN'' to the ''reset'' input (remember to invert it), and the ''segment'' and ''anode'' signals to the top-level ''segment'' and ''anode'' signals. You will need to create additional logic to control the other signals of your seven segment controller (dataIn, digitDisplay, and digitPoint). In particular, your logic will generate the values for these signals based on the values of the top-level buttons and switches. The figure below provides a high-level diagram of how you should organize your top-level design. |
| {{ :labs:seven_segment_control_top.png?nolink&500 |}} | {{ :labs:seven_segment_control_top.png?nolink&500 |}} | ||
| Line 236: | Line 245: | ||
| <color red>Summarize the size of your circuit (LUTs and FFs)</color>. | <color red>Summarize the size of your circuit (LUTs and FFs)</color>. | ||
| + | |||
| + | ===== Final Pass Off ===== | ||
| + | |||
| + | |||
| + | Pass off your laboratory by demonstrating the following to the TA: | ||
| + | * Pass offs for Exercise 1 and 2 | ||
| + | * Your working circuit on the Nexys4 board | ||
| + | |||
| + | <color red>How many hours did you work on the lab?</color> | ||
| + | |||
| + | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
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| <color red>Describe your personal exploration activities</color> | <color red>Describe your personal exploration activities</color> | ||
| - | |||
| - | |||
| - | ===== Pass Off ===== | ||
| - | |||
| - | |||
| - | Pass off your laboratory by demonstrating the following to the TA: | ||
| - | * Your testbench simulation without any errors | ||
| - | * Your working circuit on the Nexys4 board | ||
| - | |||
| - | <color red>How many hours did you work on the lab?</color> | ||
| - | |||
| - | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| /* | /* | ||
