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labs:seven_segment [2020/02/11 11:50] nelson [Preliminary] |
labs:seven_segment [2020/02/12 17:31] (current) ee220ta [Exercise #1 - Seven Segment SystemVerilog] |
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| <color red>Include your TCL simulation file in your report.</color> | <color red>Include your TCL simulation file in your report.</color> | ||
| - | **Exercise 1 Pass-off:** Show a TA your your SV code, tcl commands and simulation. \\ \\ | + | **Exercise 1 Pass-off:** Show a TA your SV code, tcl commands and simulation. \\ \\ |
