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labs:seven_segment [2019/06/28 11:28] jgoeders [Preliminary] |
labs:seven_segment [2020/02/12 17:31] (current) ee220ta [Exercise #1 - Seven Segment SystemVerilog] |
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| In this configuration, all eight LEDs share a common **anode** which enables the display. Each segment has its own **cathode** signal labeled CX where **X** represents the segment letter. For example, signal **CA** corresponds to the cathode signal for segment **a**. | In this configuration, all eight LEDs share a common **anode** which enables the display. Each segment has its own **cathode** signal labeled CX where **X** represents the segment letter. For example, signal **CA** corresponds to the cathode signal for segment **a**. | ||
| - | To turn on an LED, there must be a sufficient voltage drop from anode to cathode. Thus, two conditions are needed to turn on a segment. | + | To turn on an LED, there must be a sufficient voltage drop from anode to cathode. That is, the anode needs to have a high voltage ('1') and the cathode has to have a low voltage ('0'). |
| - | - The anode needs to have a high voltage. If the anode has a low-voltage, all of the segments will be off. | + | |
| - | - The cathode signal corresponding to that segment that is **on** needs to have a low voltage. (This creates the voltage drop necessary to turn on the LED. If the cathode signal has a high voltage, it will have the same voltage as the anode, and there will be no voltage drop. ) | + | |
| To display the character **0**, the anode signal will have a high voltage, the cathode signals CA, CB, CC, CD, CE, and CF will have a low voltage, and the cathode signal CG will have a high voltage. | To display the character **0**, the anode signal will have a high voltage, the cathode signals CA, CB, CC, CD, CE, and CF will have a low voltage, and the cathode signal CG will have a high voltage. | ||
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| ^ F | 1 | 1 | 1 | 1 | | | | | | | | | ^ F | 1 | 1 | 1 | 1 | | | | | | | | | ||
| - | zAfter filling out the table, Complete the following requirements. | + | After filling out the table, <color red>provide a logic equation for segment A (CA).</color> |
| - | <color red>Provide a minimized logic equation for segment A (CA).</color> | ||
| - | |||
| - | <color red>Provide a minimized logic equation for segment B (CB).</color> | ||
| If you're confused about how to make an equation for a segment, remember that a whole column represents an individual output. Simply pick the column for the segment as labeled in the table. | If you're confused about how to make an equation for a segment, remember that a whole column represents an individual output. Simply pick the column for the segment as labeled in the table. | ||
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| On Learning Suite, you will only fill in a few sections of this table. Make sure that your entire table is correct - it will make the rest of this lab much easier. | On Learning Suite, you will only fill in a few sections of this table. Make sure that your entire table is correct - it will make the rest of this lab much easier. | ||
| - | === Anode Signals === | + | === The Board's 7 Segments === |
| - | + | ||
| - | The seven-segment display on the NEXYS 4 board has //eight// unique digits. | + | |
| - | Each digit of the eight digit display has its own anode input. In order to turn on any of the segments of a digit, its corresponding anode signal must be asserted to provide current for individual LED segments of the digit. The schematic of this eight-digit, seven-segment display is shown below. | + | |
| - | {{ :labs:seven_segment_schematic.png?350&nolink |}} | + | The seven-segment display on the NEXYS 4 board has //eight// unique digits as shown below. |
| + | {{ :labs:7seglab_0.png?600 |}} | ||
| + | /*{{ :labs:seven_segment_schematic.png?350&nolink |}} */ | ||
| - | This eight-digit, seven-segment display configuration is known as a **common cathode** arrangement because the cathode signals are shared among all eight digits. If more than one anode signal is asserted, the corresponding digits will have the same segments turn on because they are connected to the same cathode signals. While this significantly reduces the pin count, it makes it difficult to display different values simultaneously. (Different values can be displayed by time-multiplexing the cathode signals. You will create a time-multiplexing seven segment display controller in a future laboratory assignment.) | + | Each digit of the eight digit display has its own anode input (A0-A7). |
| + | NOTE, however, that there is a built-in inverter on each anode signal. Thus, to turn on any of the segments of a digit, its corresponding anode and cathode signals must both be //driven LOW//. The schematic of this eight-digit, seven-segment display is shown below. | ||
| - | The seven-segment display in this schematic uses a dedicated transistor to drive each of the anode signals. (A transistor is used because it can provide more current than the FPGA input pin.) Eight anode signals (A0-A7) are used for each of the eight digits. The left-most digit is controlled by AN7, the second to the left digit is controlled by AN6, and so on down to the right-most digit which is controlled by AN0. Because of the way the transistor is used to drive the anode input to the seven-segment display, a logic value of **0** must be passed to the anode to turn on a digit. | + | This eight-digit, seven-segment display configuration is known as a **common cathode** arrangement because the cathode signals are shared among all eight digits. If more than one anode signal is asserted low, the corresponding digits will have the same segments turn on because they are connected to the same cathode signals. While this significantly reduces the pin count, it makes it difficult to display different values simultaneously. (Different values can be displayed by quickly switching between the various anode and cathode signals --- the LED's will flash so quickly your eye will see them as all being "on". This is called "time-multiplexing" the digits. You will be given a time-multiplexing seven segment display controller to use in future laboratory assignments.) |
| For example, to turn on only the right two digits of the eight digit display, AN1 and AN0 must have a logic value of **0** and the other anode signals must have a logic value of **1**. | For example, to turn on only the right two digits of the eight digit display, AN1 and AN0 must have a logic value of **0** and the other anode signals must have a logic value of **1**. | ||
| - | In the following example, two of the digits are turned on by setting their corresponding anode to zero. All of the other digits are off since their anode signals are set to one. In addition, the digit **3** is displayed based on which cathode signals have a logic **1**. The digit point is also on since the cathode signal, DP, associated with the digit point is set to **0**. | + | In the following example, two of the digits are turned on by setting their corresponding anode to zero. All of the other digits are off since their anode signals are set to one. In addition, the digit **3** is displayed based on which cathode signals have a logic **0**. The digit point is also on since the cathode signal, DP, associated with the digit point is set to **0**. |
| ^ A7 ^ A6 ^ A5 ^ A4 ^ A3 ^ A2 ^ A1 ^ A0 ^ | ^ A7 ^ A6 ^ A5 ^ A4 ^ A3 ^ A2 ^ A1 ^ A0 ^ | ||
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| ==== Exercise #1 - Seven Segment SystemVerilog ==== | ==== Exercise #1 - Seven Segment SystemVerilog ==== | ||
| - | In this exercise you will create a seven segment decoder in a SystemVerilog module. Begin by [[tutorials:vivado_project_setup|creating a new Vivado project]] like you did in the previous lab (you will create a new project for each laboratory assignment). | + | In this exercise you will create a seven segment decoder in a SystemVerilog module. Begin by [[tutorials:vivado_project_setup|creating a new Vivado project]] like you did in the previous lab (you will create a new project for each laboratory assignment). Remember to always follow the instructions in red to properly configure the error messages. |
| After creating this project, create a new SystemVerilog file with the following module name and ports: | After creating this project, create a new SystemVerilog file with the following module name and ports: | ||
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| | segment | Output | 7 | Cathode signals for seven segment display (excluding digit point). segment[0] corresponds to CA and segment[6] corresponds to CG | | | segment | Output | 7 | Cathode signals for seven segment display (excluding digit point). segment[0] corresponds to CA and segment[6] corresponds to CG | | ||
| - | Begin your SystemVerilog module by creating the logic for cathodes CA (segment[0]) and CB (segment[1]) using the minimized logic equations you created in the preliminary section. For these two functions, use only the standard logic gates and, not, or, etc. The input for both logic functions is the data[3:0] input bus. | + | Review the page on [[resources:combinational_logic_styles|Combinational Logic Styles]]. |
| - | + | ||
| - | It would be tedious to minimize the logic for //all// of the segments in the table you filled out earlier. Another way to implement logic for these segments is to use a **LUT** or look-up table. A LUT is essentially a truth table with 2<sup>n</sup> entries for n inputs. | + | |
| - | + | ||
| - | In the previous lab, you listed the number of LUTs that the FPGA board used to implement your program. In this lab, we will instance some LUTs directly by using an LUT4 primitive that our Xilinx Artix device contains. Think of it as a 4-input truth table where you get to declare the output directly. You will use the data[3:0] bus as the input and one column of the segment truth table as the declared output. The module definition of this primitive is as follows: | + | |
| - | + | ||
| - | <code> | + | |
| - | module LUT4 #(parameter INIT=16'h0000) (O, I0, I1, I2, I3); | + | |
| - | </code> | + | |
| - | + | ||
| - | O is the output of this module, I[3:0] are the inputs, and INIT is the parameter we will use to declare the contents of the LUT. To find this number, we just need to read it from our truth table. Bit 0 of INIT corresponds to the first row of the truth table, Bit 1 corresponds to the second row, and so on. The following example uses a LUT4 to implement the logic for segment[0] (CA). You will copy this and modify it for segment[2] through segment[6]. | + | |
| - | + | ||
| - | <code> | + | |
| - | LUT4 #(16'h2812) seg0(.O(segment[0]), .I0(data[0]), .I1(data[1]), .I2(data[2]), .I3(data[3])); | + | |
| - | </code> | + | |
| - | + | ||
| - | This is exactly like instancing one of your own modules except that the module has already been defined for this FPGA board. Note that the value ''2812'' is the column associated with segment[0] (CA), read from bottom to top and converted into hex. | + | |
| - | {{ labs:lab_4:reading_hex.png?nolink&150 }} | + | Create the logic necessary for your cathode segments (CA to CG) (For this circuit, you will not create logic for the digit point (segment[7])). |
| - | Complete the logic for your cathode segments by instancing a LUT4 for the outputs segment[2] (CC), segment[3] (CD), segment[4] (CE), segment[5] (CF), and segment[6] (CG). For this circuit, you will not create logic for the digit point (segment[7]). | + | You are required to use a mix of combinational logic styles. For your seven segments, you must have at least one segment that uses each of the following styles: |
| + | * Structural SV, in non-minimized, sum-of-products. | ||
| + | * Structural SV, optimized using the theorems in Table 4.1 of the textbook. | ||
| + | * Dataflow SV, using an assign statement and the ?: (sometimes called the ternary) operator. | ||
| + | * Dataflow SV, using an assign statement and dataflow operators of your choice (comparison, and, or, etc.) | ||
| + | * Behavioral SV, using an ''always_comb'' block, and if/else statements. | ||
| + | * Behavioral SV, using an ''always_comb'' block, and case statements. | ||
| Once you have completed the logic for your seven segment decoder, proceed with the simulation of your module using a TCL script. Your TCL file should simulate all 16 possible digits to see if the output of your module matches that seven segment decoder table from the preliminary section. | Once you have completed the logic for your seven segment decoder, proceed with the simulation of your module using a TCL script. Your TCL file should simulate all 16 possible digits to see if the output of your module matches that seven segment decoder table from the preliminary section. | ||
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| <color red>Include your TCL simulation file in your report.</color> | <color red>Include your TCL simulation file in your report.</color> | ||
| - | **Exercise 1 Pass-off:** Show a TA yout tcl commands and your simulation. Also, explain the purpose of using LUTs instead of deriving more logic equations.\\ \\ | + | **Exercise 1 Pass-off:** Show a TA your SV code, tcl commands and simulation. \\ \\ |
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| <color red>Copy and paste the testbench console output into your report (the console should report no errors).</color> | <color red>Copy and paste the testbench console output into your report (the console should report no errors).</color> | ||
| - | |||
| - | <color red>Paste the SystemVerilog code for your **seven_segment** module in your laboratory report.</color> | ||
| **Exercise 2 Pass-off:** Show a TA that your module passed the testbench without reporting any errors.\\ \\ | **Exercise 2 Pass-off:** Show a TA that your module passed the testbench without reporting any errors.\\ \\ | ||
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| After completing your top-level design, simulate your top-level design to make sure your digit point (DP) logic and your anode logic is correct. Also, simulate all possible data inputs to verify your top-level circuit is working properly. | After completing your top-level design, simulate your top-level design to make sure your digit point (DP) logic and your anode logic is correct. Also, simulate all possible data inputs to verify your top-level circuit is working properly. | ||
| - | |||
| - | <color red>Include a copy of your top-level SystemVerilog module in your laboratory report</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for the top-level module and your working simulation.\\ \\ | **Exercise 3 Pass-off:** Show a TA your code for the top-level module and your working simulation.\\ \\ | ||
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| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| - | ===== Personal Exploration ===== | + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). |
| + | ===== Personal Exploration ===== | ||
| + | There is no personal exploration this week. | ||
| + | /* | ||
| Here are some ideas for personal exploration in this laboratory: | Here are some ideas for personal exploration in this laboratory: | ||
| * Create a different seven-segment decoder that implements a different font (upside down, letters in the alphabet, your own unique character set, etc.) | * Create a different seven-segment decoder that implements a different font (upside down, letters in the alphabet, your own unique character set, etc.) | ||
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| <color red>Describe your personal exploration activities</color> | <color red>Describe your personal exploration activities</color> | ||
| + | */ | ||
| ---- | ---- | ||
| [[labs:ta:seven_segment_decoder|TA Notes and Feedback]] | [[labs:ta:seven_segment_decoder|TA Notes and Feedback]] | ||
