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labs:registerfile [2019/07/17 15:14] jgoeders [Exercise #3 - Top-level design and Testbench] |
labs:registerfile [2019/07/17 15:14] (current) jgoeders [Final Pass Off] |
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| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
