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labs:registerfile [2019/07/17 15:14] jgoeders [Exercise #2 - 8x4 Register File] |
labs:registerfile [2019/07/17 15:14] (current) jgoeders [Final Pass Off] |
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| <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | ||
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| - | <color red>Submit your top-level SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | ||
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| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
