User Tools
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
labs:registerfile [2019/05/24 11:07] jgoeders [Exercise #3 - Top-level design and Testbench] |
labs:registerfile [2019/07/17 15:14] (current) jgoeders [Final Pass Off] |
||
|---|---|---|---|
| Line 78: | Line 78: | ||
| </code> | </code> | ||
| - | |||
| - | <color red>Provide a copy of your 4-bit register SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | ||
| Line 112: | Line 110: | ||
| <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | ||
| - | |||
| - | <color red>Provide a copy of your register file SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | ||
| Line 136: | Line 132: | ||
| Instance your register_file_8x4 module you created in the previous exercise and complete the following. | Instance your register_file_8x4 module you created in the previous exercise and complete the following. | ||
| * Attach the top-level clock input to the clock port of the register file. | * Attach the top-level clock input to the clock port of the register file. | ||
| - | * Attach the top-level reset input (CPU_RESETN) to the ``reset`` port of the register file. Note: The CPU_RESETN button is active-low (0 when pressed), so you will want to connect the inverted signal (~CPU_RESETN) to the register file. | + | * Attach the top-level reset input (CPU_RESETN) to the ''reset'' port of the register file. Note: The CPU_RESETN button is active-low (0 when pressed), so you will want to connect the inverted signal (~CPU_RESETN) to the register file. |
| * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | ||
| * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | ||
| Line 155: | Line 151: | ||
| <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | ||
| - | |||
| - | <color red>Submit your top-level SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | ||
| Line 187: | Line 181: | ||
| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
