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labs:registerfile [2019/05/24 11:05] jgoeders [Exercise #2 - 8x4 Register File] |
labs:registerfile [2019/07/17 15:14] (current) jgoeders [Final Pass Off] |
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| </code> | </code> | ||
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| - | <color red>Provide a copy of your 4-bit register SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | ||
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | Clock input | | | clk | Input | 1 | Clock input | | ||
| - | | reset | Input | 1 | Reset all registers to 0 | | + | | reset | Input | 1 | Active-high reset, clears all registers | |
| | datain | Input | 4 | Data to be loaded into register file | | | datain | Input | 4 | Data to be loaded into register file | | ||
| | we | Input | 1 | Write enable | | | we | Input | 1 | Write enable | | ||
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| <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | ||
| - | |||
| - | <color red>Provide a copy of your register file SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | ||
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | Clock input | | | clk | Input | 1 | Clock input | | ||
| + | | CPU_RESETN | Input | 1 | Active-low reset, clears all registers | | ||
| | sw | Input | 10 | Switches for address input and data input | | | sw | Input | 10 | Switches for address input and data input | | ||
| | btnc | Input | 1 | Write to register file | | | btnc | Input | 1 | Write to register file | | ||
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| Instance your register_file_8x4 module you created in the previous exercise and complete the following. | Instance your register_file_8x4 module you created in the previous exercise and complete the following. | ||
| * Attach the top-level clock input to the clock port of the register file. | * Attach the top-level clock input to the clock port of the register file. | ||
| + | * Attach the top-level reset input (CPU_RESETN) to the ''reset'' port of the register file. Note: The CPU_RESETN button is active-low (0 when pressed), so you will want to connect the inverted signal (~CPU_RESETN) to the register file. | ||
| * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | ||
| * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | ||
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| <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | ||
| - | |||
| - | <color red>Submit your top-level SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | ||
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| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
