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labs:registerfile [2019/05/24 10:51] jgoeders |
labs:registerfile [2019/07/17 15:14] (current) jgoeders [Final Pass Off] |
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| For the body of this module, instance four FDCE flip-flops and complete the following steps. | For the body of this module, instance four FDCE flip-flops and complete the following steps. | ||
| * Attach the clock of each flip flop, **C**, to the 4-bit register module's **clk** signal. | * Attach the clock of each flip flop, **C**, to the 4-bit register module's **clk** signal. | ||
| + | * Attach the asynchronous clear of each flip flop, **CLR**, to the 4-bit register module's **reset** signal. | ||
| * Attach the 4-bit register's **we** signal to the **ce** input of each flip-flop. | * Attach the 4-bit register's **we** signal to the **ce** input of each flip-flop. | ||
| * Attach a different bit of **datain** to the **D** input of each FDCE flip-flop. | * Attach a different bit of **datain** to the **D** input of each FDCE flip-flop. | ||
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| <code TCL> | <code TCL> | ||
| + | restart | ||
| # run for 100ns so the FDCE can properly reset | # run for 100ns so the FDCE can properly reset | ||
| run 100 ns | run 100 ns | ||
| + | |||
| # add oscillating clock input | # add oscillating clock input | ||
| add_force clk {0 0} {1 5ns} -repeat_every 10ns | add_force clk {0 0} {1 5ns} -repeat_every 10ns | ||
| + | |||
| + | # clear value | ||
| + | add_force reset 1 | ||
| + | run 10 ns | ||
| + | add_force reset 0 | ||
| + | |||
| # initialize signals | # initialize signals | ||
| add_force we 0 | add_force we 0 | ||
| Line 69: | Line 78: | ||
| </code> | </code> | ||
| - | |||
| - | <color red>Provide a copy of your 4-bit register SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | **Exercise 1 Pass-off:** Show a TA your code for your register4 module and your simulation waveform.\\ \\ | ||
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | Clock input | | | clk | Input | 1 | Clock input | | ||
| + | | reset | Input | 1 | Active-high reset, clears all registers | | ||
| | datain | Input | 4 | Data to be loaded into register file | | | datain | Input | 4 | Data to be loaded into register file | | ||
| | we | Input | 1 | Write enable | | | we | Input | 1 | Write enable | | ||
| Line 92: | Line 100: | ||
| - Create the **Write Decoder** that generates a unique register write signal for each of the eight registers. As described in the reading, this decoder will decode write address (**waddr**) and use the **we** signal to generate a write enable for each register. | - Create the **Write Decoder** that generates a unique register write signal for each of the eight registers. As described in the reading, this decoder will decode write address (**waddr**) and use the **we** signal to generate a write enable for each register. | ||
| - Instance eight of the 4-bit registers that you created in the previous exercise. These eight registers form the core of the register file module. | - Instance eight of the 4-bit registers that you created in the previous exercise. These eight registers form the core of the register file module. | ||
| - | - Attach the clock input to all eight registers and the **datain** signal to the input to each register. | + | - Attach the clock and reset inputs to all eight registers and the **datain** signal to the input to each register. |
| - Create two 8:1 multiplixers for the read ports. | - Create two 8:1 multiplixers for the read ports. | ||
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| <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | ||
| - | |||
| - | <color red>Provide a copy of your register file SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | **Exercise 2 Pass-off:** Show a TA your code for your register8x4 module and your simulation waveform. Show that your tcl file meets the requirements listed above.\\ \\ | ||
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | Clock input | | | clk | Input | 1 | Clock input | | ||
| + | | CPU_RESETN | Input | 1 | Active-low reset, clears all registers | | ||
| | sw | Input | 10 | Switches for address input and data input | | | sw | Input | 10 | Switches for address input and data input | | ||
| | btnc | Input | 1 | Write to register file | | | btnc | Input | 1 | Write to register file | | ||
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| Instance your register_file_8x4 module you created in the previous exercise and complete the following. | Instance your register_file_8x4 module you created in the previous exercise and complete the following. | ||
| * Attach the top-level clock input to the clock port of the register file. | * Attach the top-level clock input to the clock port of the register file. | ||
| + | * Attach the top-level reset input (CPU_RESETN) to the ''reset'' port of the register file. Note: The CPU_RESETN button is active-low (0 when pressed), so you will want to connect the inverted signal (~CPU_RESETN) to the register file. | ||
| * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | * Attach the **btnc** input to the **we** input of the register file (the center button will be used to write new values into the register file). | ||
| * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | * Attach **sw[3:0]** to the **datain** input of the register file. The lower four switches will be used to set the data that is written into the register file. | ||
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| <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | <color red>Copy the console output for your testbench simulation and add it to your laboratory report.</color> | ||
| - | |||
| - | <color red>Submit your top-level SystemVerilog code in your laboratory report.</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | **Exercise 3 Pass-off:** Show a TA your code for your top level module and your testbench output.\\ \\ | ||
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| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
