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| Both sides previous revision Previous revision | |||
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labs:pong_part_1 [2019/11/10 18:49] jgoeders [Exercise #1 - BallDrawer State Machine] |
labs:pong_part_1 [2019/11/15 10:30] (current) jgoeders [Exercise #2 - BallDrawer SystemVerilog Module] |
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| Line 93: | Line 93: | ||
| add_force clk {0 0} {1 5ns} -repeat_every 10ns | add_force clk {0 0} {1 5ns} -repeat_every 10ns | ||
| add_force reset 1 | add_force reset 1 | ||
| + | add_force start 0 | ||
| run 10ns | run 10ns | ||
| add_force reset 0 | add_force reset 0 | ||
