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labs:pong_part_1 [2019/11/10 09:16] jgoeders [Final Pass-Off] |
labs:pong_part_1 [2019/11/15 10:30] (current) jgoeders [Exercise #2 - BallDrawer SystemVerilog Module] |
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| * The state machine should wait for the ''start'' signal before starting to draw a ball. | * The state machine should wait for the ''start'' signal before starting to draw a ball. | ||
| * For each pixel that needs to be drawn, the state machine should output an (x,y) coordinate using the ''x_out'' and ''y_out'' outputs, and assert the ''draw'' signal to indicate that a valid pixel is being output. | * For each pixel that needs to be drawn, the state machine should output an (x,y) coordinate using the ''x_out'' and ''y_out'' outputs, and assert the ''draw'' signal to indicate that a valid pixel is being output. | ||
| - | * The ''done'' signal should be asserted after the ball is done being drawn (or on the last pixel). | + | * The ''done'' signal should be asserted for exactly 1 cycle after the ball is done being drawn (or during the last pixel). |
| * The state machine should wait for the ''start'' signal to go low before allowing another ball to be drawn. | * The state machine should wait for the ''start'' signal to go low before allowing another ball to be drawn. | ||
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| add_force clk {0 0} {1 5ns} -repeat_every 10ns | add_force clk {0 0} {1 5ns} -repeat_every 10ns | ||
| add_force reset 1 | add_force reset 1 | ||
| + | add_force start 0 | ||
| run 10ns | run 10ns | ||
| add_force reset 0 | add_force reset 0 | ||
| Line 174: | Line 175: | ||
| <color red>Submit your final lab report on Learning Suite. Submit the SystemVerilog code of your two modules.</color> | <color red>Submit your final lab report on Learning Suite. Submit the SystemVerilog code of your two modules.</color> | ||
| + | There is no personal exploration for this lab. | ||
