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labs:pong_part_1 [2019/11/10 09:07] jgoeders [Exercise #1 - BallDrawer State Machine] |
labs:pong_part_1 [2019/11/15 10:30] (current) jgoeders [Exercise #2 - BallDrawer SystemVerilog Module] |
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| {{:labs:lab_pong:ball_drawing_5.png| }} | {{:labs:lab_pong:ball_drawing_5.png| }} | ||
| - | |||
| {{:labs:lab_pong:ball_drawing2.png| }} | {{:labs:lab_pong:ball_drawing2.png| }} | ||
| Your state machine does not need to produce the exact same timing as the waveform above, but it does not to obey a few rules: | Your state machine does not need to produce the exact same timing as the waveform above, but it does not to obey a few rules: | ||
| * The state machine should wait for the ''start'' signal before starting to draw a ball. | * The state machine should wait for the ''start'' signal before starting to draw a ball. | ||
| - | * For each pixel that needs to be drawn, the state machine should output an (x,y) coordinate using the ''x_out'' and ''y_out'' outputs, and assert the ''draw_enable'' signal. | + | * For each pixel that needs to be drawn, the state machine should output an (x,y) coordinate using the ''x_out'' and ''y_out'' outputs, and assert the ''draw'' signal to indicate that a valid pixel is being output. |
| - | * The ''done'' signal should be asserted after the ball is done being drawn (or on the last pixel). | + | * The ''done'' signal should be asserted for exactly 1 cycle after the ball is done being drawn (or during the last pixel). |
| * The state machine should wait for the ''start'' signal to go low before allowing another ball to be drawn. | * The state machine should wait for the ''start'' signal to go low before allowing another ball to be drawn. | ||
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| add_force clk {0 0} {1 5ns} -repeat_every 10ns | add_force clk {0 0} {1 5ns} -repeat_every 10ns | ||
| add_force reset 1 | add_force reset 1 | ||
| + | add_force start 0 | ||
| run 10ns | run 10ns | ||
| add_force reset 0 | add_force reset 0 | ||
| Line 114: | Line 114: | ||
| run 120ns | run 120ns | ||
| </file> | </file> | ||
| - | |||
| - | <color #ed1c24>Include a copy of your TCL file in your lab report.</color> | ||
| Line 154: | Line 152: | ||
| | y_out | Output | 8 | y-Coordinate to be drawn | | | y_out | Output | 8 | y-Coordinate to be drawn | | ||
| - | This module should work very similarly to your ''BallDrawer'' module, except now there is a ''height'' input that dictates the height of the line. You should use a counter to keep track of how many pixels you need to draw. | + | This module should work very similarly to your ''BallDrawer'' module, except now there is a ''height'' input that dictates the height of the line. Since the height can be changed, you can't use one state per pixel being drawn. Instead, your state machine will need to interact with a counter to keep track of how many pixels you need to draw. |
| - | The following shows a diagram of a line 6 pixels tall, and the corresponding waveform for drawing this line at (100, 50). | + | The following shows a diagram of a line 6 pixels tall, and a waveform for drawing this line at (100, 50). |
| {{:labs:lab_pong:line_drawing.png |}} | {{:labs:lab_pong:line_drawing.png |}} | ||
| Line 162: | Line 160: | ||
| {{:labs:lab_pong:line_drawing_waveform.png|}} | {{:labs:lab_pong:line_drawing_waveform.png|}} | ||
| - | Simulate your ''VLineDrawer'' module to ensure it is working correctly. You can probably re-use the TCL above, but make sure to set the ''height'' input. | + | Simulate your ''VLineDrawer'' module to ensure it is working correctly. You can probably re-use the TCL above with minimal changes. Make sure to set the ''height'' input, and test drawing two lines of different height. |
| + | |||
| + | <color #ed1c24>Paste your TCL simulation file in your lab report.</color> | ||
| Modify the top-level from the last exercise to draw a vertical line instead of a ball. | Modify the top-level from the last exercise to draw a vertical line instead of a ball. | ||
| Line 169: | Line 169: | ||
| ** Exercise #4 Pass-off:** Show the TA your ''VLineDrawer'' module and the line drawing correctly on the monitor. | ** Exercise #4 Pass-off:** Show the TA your ''VLineDrawer'' module and the line drawing correctly on the monitor. | ||
| - | <color red>Submit your final lab report on Learning Suite.</color> | + | ---- |
| + | |||
| + | ==== Final Pass-Off === | ||
| + | |||
| + | <color red>Submit your final lab report on Learning Suite. Submit the SystemVerilog code of your two modules.</color> | ||
| + | There is no personal exploration for this lab. | ||
