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labs:funwithregisters [2019/10/11 11:09] nelson [Exercise #4: Synthesize, Implement, and Test in Hardware] |
labs:funwithregisters [2020/04/28 17:02] (current) nelson old revision restored (2020/02/14 13:11) |
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| - | ====== Under Development: Lab 5 - Fun With Registers ====== | + | ====== Lab 6 - Fun With Registers ====== |
| + | === Prof Brent Nelson === | ||
| In this lab you will do some experimentation with flip flops to learn how they operate. You will create a single-bit loadable register, a 4-bit loadable register, and a counter. | In this lab you will do some experimentation with flip flops to learn how they operate. You will create a single-bit loadable register, a 4-bit loadable register, and a counter. | ||
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| ==== Exercise #1 - 1-Bit Register ==== | ==== Exercise #1 - 1-Bit Register ==== | ||
| - | For this exercise you will create a 1-bit register. It is exactly the circuit in Figure 16.4 in the textbook. Begin this exercise by creating an empty SystemVerilog module with the following name and ports. | + | For this exercise you will create a 1-bit register. It is exactly the circuit in Figure 16.4 in the textbook. Begin this exercise by creating a new Vivado project and an empty SystemVerilog module with the following name and ports. |
| - | ^ Module Name: blinky ^^^^ | + | ^ Module Name: funRegister ^^^^ |
| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | CLK | Input | 1 | Clock input | | | CLK | Input | 1 | Clock input | | ||
| - | | D | Input | 1 | Data to be loaded into register | | + | | DIN | Input | 1 | Data to be loaded into register | |
| | LOAD | Input | 1 | Control signal to cause register to load | | | LOAD | Input | 1 | Control signal to cause register to load | | ||
| | Q | Output | 1 | Register output | | | Q | Output | 1 | Register output | | ||
| Line 43: | Line 44: | ||
| so we can watch it. | so we can watch it. | ||
| - | Then, instance one FDCE flip-flop as shown above. Then, add either a single dataflow statement or an always_comb block to implement the MUX logic. You should now have logic which implements the MUX and have the MUX wired to the ports on the FDCE. This is called a "loadable register". On each rising edge of CLK, If LOAD is high, then the flip flop will load what is on its D input. On the other hand, if LOAD is low, then the flip flop will load its old value. | + | Then, instance one FDCE flip-flop as shown above. Then, add either a single dataflow statement or an always_comb block to implement the MUX logic. You should now have logic which implements the MUX and have the MUX wired to the ports on the FDCE. This is called a "loadable register". On each rising edge of CLK, If LOAD is high, then the flip flop will load what is on its DIN input. On the other hand, if LOAD is low, then the flip flop will load its old value. |
| SANITY CHECK: your code should have approximately 5 lines. If it has a lot more you are likely on the wrong track... | SANITY CHECK: your code should have approximately 5 lines. If it has a lot more you are likely on the wrong track... | ||
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| # set inputs low | # set inputs low | ||
| add_force LOAD 0 | add_force LOAD 0 | ||
| - | add_force D 0 | + | add_force DIN 0 |
| # add oscillating clock input with 10ns period | # add oscillating clock input with 10ns period | ||
| Line 72: | Line 73: | ||
| add_force LOAD 0 | add_force LOAD 0 | ||
| - | # change D and run some time | + | # change DIN and run some time |
| # notice that the register doesn't | # notice that the register doesn't | ||
| # load this new value because | # load this new value because | ||
| # the load signal is low | # the load signal is low | ||
| - | add_force D 1 | + | add_force DIN 1 |
| run 20ns | run 20ns | ||
| Line 83: | Line 84: | ||
| run 10ns | run 10ns | ||
| add_force LOAD 0 | add_force LOAD 0 | ||
| - | add_force D 0 | + | add_force DIN 0 |
| run 10ns | run 10ns | ||
| Line 90: | Line 91: | ||
| # the register load them | # the register load them | ||
| # on succeeding clock edges | # on succeeding clock edges | ||
| - | add_force D 1 | + | add_force DIN 1 |
| run 10ns | run 10ns | ||
| add_force LOAD 1 | add_force LOAD 1 | ||
| run 10ns | run 10ns | ||
| - | add_force D 0 | + | add_force DIN 0 |
| run 10ns | run 10ns | ||
| run 10ns | run 10ns | ||
| run 10ns | run 10ns | ||
| - | add_force D 1 | + | add_force DIN 1 |
| run 10ns | run 10ns | ||
| run 10ns | run 10ns | ||
| - | add_force D 0 | + | add_force DIN 0 |
| </code> | </code> | ||
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| **Exercise 1 Pass-off:** No need to pass off this. Just make sure it works in simulation before you proceed.\\ \\ | **Exercise 1 Pass-off:** No need to pass off this. Just make sure it works in simulation before you proceed.\\ \\ | ||
| - | ==== Exercise #2 - 4-bit Register File ==== | + | ==== Exercise #2 - 4-bit Register ==== |
| In this exercise, you will modify your register to be 4 bits wide as shown in Figure 16.5 | In this exercise, you will modify your register to be 4 bits wide as shown in Figure 16.5 | ||
| of the textbook. To do this the changes to your code are minimal: (a) | of the textbook. To do this the changes to your code are minimal: (a) | ||
| - | make the D, NXT, and Q signals 4 bits wide in your module definition and (b) instance a total of 4 FDCE flip flops and wire them up like the one in Exercise #1. If you have used a ?: operator or an if-then-else statement to describe your MUX you probably shouldn't even have to change the MUX code. | + | make the DIN, NXT, and Q signals 4 bits wide in your module definition and (b) instance a total of 4 FDCE flip flops and wire them up like the one in Exercise #1. If you have used a ?: operator or an if-then-else statement to describe your MUX you probably shouldn't even have to change the MUX code. |
| - | After creating your register, simulate it by modifying your original TCL script. The only changes that you should have to make are to change the 1 and 0 values you drive into D to be more interesting numbers between 0000 and 1111. | + | After creating your register, simulate it by modifying your original TCL script. The only changes that you should have to make are to change the 1 and 0 values you drive into DIN to be more interesting numbers between 0000 and 1111. |
| - | <color red>Provide a copy of your TCL script you used to simulate the register file.</color> | + | <color red>Provide a copy of your TCL script you used to simulate the 4-bit register.</color> |
| **Exercise 2 Pass-off:** Show a TA your code for your 4-bit register | **Exercise 2 Pass-off:** Show a TA your code for your 4-bit register | ||
| and your simulation waveform. Show that your register loads 4-bit | and your simulation waveform. Show that your register loads 4-bit | ||
| - | values from D when LOAD=1 and keeps its old value otherwise. Also | + | values from DIN when LOAD=1 and keeps its old value otherwise. Also |
| show that the NXT signal does indeed reflect what the output of the | show that the NXT signal does indeed reflect what the output of the | ||
| MUX value should be. \\ \\ | MUX value should be. \\ \\ | ||
| - | ==== Exercise 3 ==== | + | ==== Exercise #3 ==== |
| We are now going to modify your 4-bit register to create a counter and use the counter to blink some lights. | We are now going to modify your 4-bit register to create a counter and use the counter to blink some lights. | ||
| In addition to making registers to hold values, another good use of registers is to create counters. Figure 16.7 from the textbook shows such a counter. It can be cleared and it can be incremented under control of the signals CLR and INC. | In addition to making registers to hold values, another good use of registers is to create counters. Figure 16.7 from the textbook shows such a counter. It can be cleared and it can be incremented under control of the signals CLR and INC. | ||
| - | ^ Module Name: blinky ^^^^ | + | ^ Module Name: funRegister ^^^^ |
| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | CLK | Input | 1 | Clock input | | | CLK | Input | 1 | Clock input | | ||
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| * Change your module definition to reflect the signals in the table above. | * Change your module definition to reflect the signals in the table above. | ||
| - | * Create combinational logic using a ?: assignment which implements the MUX of Figure 16.7 in the textbook. | + | * Create combinational logic using either a ?: dataflow assignment or an always_comb if statement to implement the MUX of Figure 16.7 in the textbook. |
| * Wire the MUX up to the register's input and output wires. | * Wire the MUX up to the register's input and output wires. | ||
| Modify your TCL script from above to exercise the counter. First, clear the counter and then increment for a few cycles. Then, clear it again and then increment it 20 or so cycles. Raise and lower INC as you do this to observe that it only counts on rising clock edges where INC is true. Finally, increment it enough times so that it then rolls back over to 0. | Modify your TCL script from above to exercise the counter. First, clear the counter and then increment for a few cycles. Then, clear it again and then increment it 20 or so cycles. Raise and lower INC as you do this to observe that it only counts on rising clock edges where INC is true. Finally, increment it enough times so that it then rolls back over to 0. | ||
| + | |||
| + | <color red>Provide a copy of your TCL script you used to simulate the counter.</color> | ||
| **Exercise 3 Pass-off:** Show a TA your code for your 4-bit counter | **Exercise 3 Pass-off:** Show a TA your code for your 4-bit counter | ||
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| | Q | Output | 4 | Tie to led3-led0 | | | Q | Output | 4 | Tie to led3-led0 | | ||
| | NXT | Output | 4 | Tie to led11-led8 | | | NXT | Output | 4 | Tie to led11-led8 | | ||
| + | |||
| + | **Note**: Your constraints file will instruct Vivado to connect the ''CLK'' to a button; however, Vivado knows that this is not a true clock pin and will report an error. In order to ignore this, you will need to add the following line to your constraints file, which you can add immediately after the constraint that connects ''CLK'' to the button: | ||
| + | |||
| + | ''set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF];'' | ||
| + | |||
| + | Even with this inserted you will get a Critical Warning, which you can ignore (at least it is now a warning and not an error). | ||
| Perform the steps of Synthesis, Implementation, and Bitstream | Perform the steps of Synthesis, Implementation, and Bitstream | ||
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| of 1 plus the new Q value. | of 1 plus the new Q value. | ||
| - | NOTE: This is the only lab we will do where we will tie the CLK input to a button. | + | NOTE: This is the only lab where we will tie the CLK input to a button. |
| In all later labs it will be tied to a 100MHz input to the FPGA. | In all later labs it will be tied to a 100MHz input to the FPGA. | ||
| You may notice that, in actuality, your counter may increment more than once when you | You may notice that, in actuality, your counter may increment more than once when you | ||
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| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
| - | Here are some ideas for personal exploration in this laboratory: | + | Choose one of the following for personal exploration in this laboratory: |
| * Make your counter wider and wire up to additional LEDs. | * Make your counter wider and wire up to additional LEDs. | ||
| - | * Wire in a copy of your 7-segment decoder from last week and have the 4-bit counter value displayed on the 7-segment display. By the way, this is way cooler than just making your counter wider... | + | * Wire in a copy of your 7-segment decoder from last week and have the 4-bit counter value displayed on the 7-segment display. By the way, this is way cooler than just making your counter wider... :-) |
| <color red>Describe your personal exploration activities.</color> | <color red>Describe your personal exploration activities.</color> | ||
