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--- labs:funwithregisters [2019/10/11 11:06]
nelson [Exercise #4: Synthesize, Implement, and Test in Hardware]
+++ labs:funwithregisters [2020/04/28 17:02] (current)
nelson old revision restored (2020/02/14 13:11)
@@ Line 1: / Line 1: @@
-====== Under Development: Lab 5 - Fun With Registers ======
+====== Lab 6 - Fun With Registers ======
+=== Prof Brent Nelson ===
 In this lab you will do some experimentation with flip flops to learn how they operate.  You will create a single-bit loadable register, a 4-bit loadable register, and a counter.
@@ Line 25: / Line 26: @@
 ==== Exercise #1 - 1-Bit Register ====
-For this exercise you will create a 1-bit register. It is exactly the circuit in Figure 16.4 in the textbook.  Begin this exercise by creating an empty SystemVerilog module with the following name and ports.
+For this exercise you will create a 1-bit register. It is exactly the circuit in Figure 16.4 in the textbook.  Begin this exercise by creating a new Vivado project and an empty SystemVerilog module with the following name and ports.
-^ Module Name: blinky ^^^^
+^ Module Name: funRegister ^^^^
 ^ Port Name ^ Direction ^ Width ^ Function ^
 | CLK | Input | 1 | Clock input |
-| D | Input | 1 | Data to be loaded into register |
+| DIN | Input | 1 | Data to be loaded into register |
 | LOAD | Input | 1 | Control signal to cause register to load |
 | Q | Output | 1 | Register output |
@@ Line 43: / Line 44: @@
 so we can watch it.
-Then, instance one FDCE flip-flop as shown above.  Then, add either a single dataflow statement or an always_comb block to implement the MUX logic. You should now have logic which implements the MUX and have the MUX wired to the ports on the FDCE.   This is called a "loadable register".  On each rising edge of CLK, If LOAD is high, then the flip flop will load what is on its D input.  On the other hand, if LOAD is low, then the flip flop will load its old value.
+Then, instance one FDCE flip-flop as shown above.  Then, add either a single dataflow statement or an always_comb block to implement the MUX logic. You should now have logic which implements the MUX and have the MUX wired to the ports on the FDCE.   This is called a "loadable register".  On each rising edge of CLK, If LOAD is high, then the flip flop will load what is on its DIN input.  On the other hand, if LOAD is low, then the flip flop will load its old value.
 SANITY CHECK: your code should have approximately 5 lines.  If it has a lot more you are likely on the wrong track...
@@ Line 59: / Line 60: @@
 # set inputs low
 add_force LOAD 0
-add_force D 0
+add_force DIN 0
 # add oscillating clock input with 10ns period
@@ Line 72: / Line 73: @@
 add_force LOAD 0
-# change D and run some time
+# change DIN and run some time
 # notice that the register doesn't
 # load this new value because
 # the load signal is low
-add_force D 1
+add_force DIN 1
 run 20ns
@@ Line 83: / Line 84: @@
 run 10ns
 add_force LOAD 0
-add_force D 0
+add_force DIN 0
 run 10ns
@@ Line 90: / Line 91: @@
 # the register load them
 # on succeeding clock edges
-add_force D 1
+add_force DIN 1
 run 10ns
 add_force LOAD 1
 run 10ns
-add_force D 0
+add_force DIN 0
 run 10ns
 run 10ns
 run 10ns
-add_force D 1
+add_force DIN 1
 run 10ns
 run 10ns
-add_force D 0
+add_force DIN 0
 </code>
@@ Line 107: / Line 108: @@
 **Exercise 1 Pass-off:** No need to pass off this.  Just make sure it works in simulation before you proceed.\\ \\
-==== Exercise #2 - 4-bit Register File ====
+==== Exercise #2 - 4-bit Register ====
 In this exercise, you will modify your register to be 4 bits wide as shown in Figure 16.5
 of the textbook.  To do this the changes to your code are minimal: (a)
-make the D, NXT, and Q signals 4 bits wide in your module definition and (b) instance a total of 4 FDCE flip flops and wire them up like the one in Exercise #1.  If you have used a ?: operator or an if-then-else statement to describe your MUX you probably shouldn't even have to change the MUX code.
+make the DIN, NXT, and Q signals 4 bits wide in your module definition and (b) instance a total of 4 FDCE flip flops and wire them up like the one in Exercise #1.  If you have used a ?: operator or an if-then-else statement to describe your MUX you probably shouldn't even have to change the MUX code.
-After creating your register, simulate it by modifying your original TCL script. The only changes that you should have to make are to change the 1 and 0 values you drive into D to be more interesting numbers between 0000 and 1111.
+After creating your register, simulate it by modifying your original TCL script. The only changes that you should have to make are to change the 1 and 0 values you drive into DIN to be more interesting numbers between 0000 and 1111.
-<color red>Provide a copy of your TCL script you used to simulate the register file.</color>
+<color red>Provide a copy of your TCL script you used to simulate the 4-bit register.</color>
 **Exercise 2 Pass-off:** Show a TA your code for your 4-bit register
 and your simulation waveform. Show that your register loads 4-bit
-values from D when LOAD=1 and keeps its old value otherwise.  Also
+values from DIN when LOAD=1 and keeps its old value otherwise.  Also
 show that the NXT signal does indeed reflect what the output of the
 MUX value should be. \\ \\
-==== Exercise 3 ====
+==== Exercise #3 ====
 We are now going to modify your 4-bit register to create a counter and use the counter to blink some lights.
 In addition to making registers to hold values, another good use of registers is to create counters.  Figure 16.7 from the textbook shows such a counter.  It can be cleared and it can be incremented under control of the signals CLR and INC.
-^ Module Name: blinky ^^^^
+^ Module Name: funRegister ^^^^
 ^ Port Name ^ Direction ^ Width ^ Function ^
 | CLK | Input | 1 | Clock input |
@@ Line 140: / Line 141: @@
   * Change your module definition to reflect the signals in the table above.
-  * Create combinational logic using a ?: assignment which implements the MUX of Figure 16.7 in the textbook.
+  * Create combinational logic using either a ?: dataflow assignment or an always_comb if statement to implement the MUX of Figure 16.7 in the textbook.
   * Wire the MUX up to the register's input and output wires.
 Modify your TCL script from above to exercise the counter.  First, clear the counter and then increment for a few cycles.  Then, clear it again and then increment it 20 or so cycles.  Raise and lower INC as you do this to observe that it only counts on rising clock edges where INC is true.  Finally, increment it enough times so that it then rolls back over to 0.
+<color red>Provide a copy of your TCL script you used to simulate the counter.</color>
 **Exercise 3 Pass-off:** Show a TA your code for your 4-bit counter
@@ Line 161: / Line 164: @@
 | INC | Input | 1 | Tie to switch 1 |
 | Q | Output | 4 | Tie to led3-led0 |
-| NXT | Output | 4 | Tie to led7-led4 |
+| NXT | Output | 4 | Tie to led11-led8 |
+**Note**:  Your constraints file will instruct Vivado to connect the ''CLK'' to a button; however, Vivado knows that this is not a true clock pin and will report an error.  In order to ignore this, you will need to add the following line to your constraints file, which you can add immediately after the constraint that connects ''CLK'' to the button:
+''set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF];''
+Even with this inserted you will get a Critical Warning, which you can ignore (at least it is now a warning and not an error).
 Perform the steps of Synthesis, Implementation, and Bitstream
@@ Line 173: / Line 182: @@
 of 1 plus the new Q value.
-NOTE: This is the only lab we will do where we will tie the CLK input to a button.
+NOTE: This is the only lab where we will tie the CLK input to a button.
 In all later labs it will be tied to a 100MHz input to the FPGA.
 You may notice that, in actuality, your counter may increment more than once when you
@@ Line 180: / Line 189: @@
 don't transition cleanly from open to closed or from closed to open.
 As they are opening or closing they may "bounce", meaning they may
-open and close rapidly in succession.  Thus, when tyou push your CLK
+open and close rapidly in succession.  Thus, when you push your CLK
 button the circuit might actually get multiple clock edges like this:
--1-0-1-0-1.  In that case your circuit would see 3 rising clock
+-1-0-1-0-1-0.  In that case your circuit would see 3 rising clock
-edges and your counter would increment by 1.  At other times it might
+edges and your counter would increment by 3.  At other times it might
-just go 0-1 and your counter will increment by 1.  Experiment with it
+just go 0-1-0 and your counter will increment by 1.  Experiment with it
 to see just how "bouncy" the button is on the board you are using.  It
 might be pretty bad or it might hardly ever bounce.  In a later lab we
@@ Line 205: / Line 214: @@
 ===== Personal Exploration =====
-Here are some ideas for personal exploration in this laboratory:
+Choose one of the following for personal exploration in this laboratory:
   * Make your counter wider and wire up to additional LEDs.
-  * Wire in a copy of your 7-segment decoder from last week and have the 4-bit counter value displayed on the 7-segment display.  By the way, this is way cooler than just making your counter wider...
+  * Wire in a copy of your 7-segment decoder from last week and have the 4-bit counter value displayed on the 7-segment display.  By the way, this is way cooler than just making your counter wider...  :-)
 <color red>Describe your personal exploration activities.</color>
@@ Line 244: / Line 253: @@
 [[labs:ta:registerfile|TA Notes and Feedback]]
-====== Under Development: Lab 5 - Fun With Registers ======
-In this lab you will do some experimentation with flip flops to learn how they operate.  You will create a single-bit loadable register, a 4-bit loadable register, and a counter.
-===== Learning Outcomes =====
-  * Create a sequential circuit using FDCE flip-flop primitives
-  * Learn how to organize multiple flip-flops into a register
-  * Create a clearable counter
-===== Preliminary =====
-The Artix-7 FPGA we are using has built-in flip-flops that you can use to make sequential circuits. You will use FDCE flip-flop primitives to construct a few simple register-type circuits.  The FDCE flip-flop is available to you without any extra work required on your part, you merely need to instance it into your design the same way you instance your own modules into your designs. Read the following pdf file to learn about the FDCE module, its ports, and how to instance the module in your SystemVerilog.
-{{ :tutorials:fdce.pdf |}}
-The SystemVerilog example below demonstrates how to instance a single FDCE flip-flop into a design:
-<code>
-FDCE my_ff (.Q(ff_output), .C(clk), .CE(1'b1), .CLR(1'b0), .D(ff_input));
-</code>
-The example shown above assigns a constant zero to the CLR input and a constant one to the clock_enable since we will not use those functions.  As a result, what you are getting is basically a flip flop with a D input, a clock input (C), and a Q output.  NOTE: this is a rising edge triggered flip flop.
-===== Exercises =====
-==== Exercise #1 - 1-Bit Register ====
-For this exercise you will create a 1-bit register. It is exactly the circuit in Figure 16.4 in the textbook.  Begin this exercise by creating an empty SystemVerilog module with the following name and ports.
-^ Module Name: blinky ^^^^
-^ Port Name ^ Direction ^ Width ^ Function ^
-| clk | Input | 1 | Clock input |
-| D | Input | 1 | Data to be loaded into register |
-| LOAD | Input | 1 | Control signal to cause register to load |
-| Q | Output | 1 | Register output |
-Note that in Figure 16.4 there is an unlabelled signal --- it is the output of the MUX (which is also the input to the flip flop).  So, declare a logic signal for that wire.  Then, instance one FDCE flip-flop as shown above.  Then, add either a single dataflow statement or an always_comb block to implement the MUX logic. You should now have logic which implements the MUX and have the MUX wired to the ports on the FDCE.   This is called a "loadable register".  On each rising edge of clk, If LOAD is high, then the flip flop will load what is on its D input.  On the other hand, if LOAD is low, then the flip flop will load its old value.
-SANITY CHECK: your code should have approximately 5 lines.  If it has a lot more you are likely on the wrong track...
-After creating your register, simulate your register with a TCL script. The following
-set of TCL commands demonstrates a simple test for your register file. You can use this script and add to or modify it to test your register as you like.
-Make sure that your TCL file includes a ''run 100ns'' at the beginning. For the first 100ns, the FDCE primitive resets itself. During this time it won't operate at all, so wait for this time to be over.
-<code TCL>
-restart
-# run for 100ns so the FDCE can properly reset
-run 100 ns
-# set inputs low
-add_force LOAD 0
-add_force D 0
-# add oscillating clock input with 10ns period
-add_force clk {0 0} {1 5ns} -repeat_every 10ns
-# run 2ns so that input changes below are not
-# coincident with clock edges.  Otherwise, the
-# waveforms are hard to understand
-run 2ns
-# run 3 cycles before loading anything
-run 30 ns
-# load a 0
-add_force LOAD 1
-run 20ns
-add_force LOAD 0
-# change D and run some time
-# notice that the register doesn't
-# load this new value because
-# the load signal is low
-add_force D 1
-run 20ns
-# now let's load the register
-add_force LOAD 1
-run 10ns
-add_force LOAD 0
-add_force D 0
-run 10ns
-# now we will apply various
-# data input values and watch
-# the register load them
-# on succeeding clock edges
-add_force D 1
-run 10ns
-add_force LOAD 1
-run 10ns
-add_force D 0
-run 10ns
-run 10ns
-run 10ns
-add_force D 1
-run 10ns
-run 10ns
-add_force D 0
-</code>
-**Exercise 1 Pass-off:** No need to pass off this.  Just make sure it works in simulation before you proceed.\\ \\
-==== Exercise #2 - 4-bit Register File ====
-In this exercise, you will modify your register to be 4 bits wide as shown in Figure 16.5
-of the textbook.  To do this the changes to your code are minimal: (a) make the D and Q signals 4 bits wide in your module definition and (b) instance a total of 4 FDCE flip flops and wire them up like the one in Exercise #1.  If you have used a ?: operator or an if-then-else statement to describe your MUX you probably shouldn't even have to change the MUX code.
-After creating your register, simulate it by modifying your original TCL script. The only changes that you should have to make are to change the 1 and 0 values you drive into D to be more interesting numbers between 0000 and 1111.
-<color red>Provide a copy of your TCL script you used to simulate the register file.</color>
-**Exercise 2 Pass-off:** Show a TA your code for your 4-bit register and your simulation waveform. Show that your register loads 4-bit values from D when LOAD=1 and keeps its old value otherwise.\\ \\
-==== Exercise 3 ====
-We are now going to modify your 4-bit register to create a counter and use the counter to blink some lights.
-In addition to making registers to hold values, another good use of registers is to create counters.  Figure 16.7 from the textbook shows such a counter.  It can be cleared and it can be incremented under control of the signals CLR and INC.
-^ Module Name: blinky ^^^^
-^ Port Name ^ Direction ^ Width ^ Function ^
-| clk | Input | 1 | Clock input |
-| CLR | Input | 1 | Clear control signal |
-| INC | Input | 1 | Increment control signal |
-| Q | Output | 4 | 4 bits of counter's register |
-Modify your design (erase the old stuff you don't need and add the new stuff):
-  * Change your module definition to reflect the signals in the table above.
-  * Create combinational logic using a ?: assignment which implements the MUX of Figure 16.7 in the textbook.
-  * Wire the MUX up to the register's input and output wires.
-Modify your TCL script from above to exercise the counter.  First, clear the counter and then increment for a few cycles.  Then, clear it again and then increment it 20 or so cycles.  Raise and lower INC as you do this to observe that it only counts on rising clock edges where INC is true.  Finally, increment it enough times so that it then rolls back over to 0.
-**Exercise 3 Pass-off:** Show a TA your code for your 4-bit counter and your simulation waveform. Show that your counter works as desired.\\ \\
-==== Exercise #4: Synthesize, Implement, and Test in Hardware ====
-You are almost ready to synthesize, implement, and test in hardware.  However, before doing so there is one more thing that must be done.
-In simulation it was easy to raise INC high for one clock cycle and then lower it again to get the counter to increment by just one.  When you download your circuit to the board and then push the INC button you will end up holding it down for millions of clock cycles.  Thus, each time you push the button in real life it will increment many many times.  To fix this, we need to condition the signal so that each time you push the button the counter will increment exactly once.
-The figure below shows what we want.
-{{ :labs:edge.png?nolink&680 |}}
-Notice that when the INC button signal goes from low to high, the CleanInc signal pulses high for exactly one clock cycle (independent of how long INC stays high).  This is what we want.  However, you don't know quite enough to design the circuit to do this and so one has been made available to you.  It has the following interface:
-^ Module Name: clean ^^^^
-^ Port Name ^ Direction ^ Width ^ Function ^
-| clk | Input | 1 | Clock input |
-| b | Input | 1 | The button signal (INC in the waveform above) |
-| bo | Output | 1 | The cleaned up button signal (CleanInc in the waveform above) |
-| Q | Output | 4 | 4 bits of counter's register |
-You can get the file {{ :labs:clean.sv | here}}.  Save it as "clean.sv" and add it to your project.
-Now, instance it like this:
-  clean C0(.clk(clk), .b(INC), .bo(CleanInc));
-Then, you need to modify what is driving the MUX select line.  Instead of INC, you now want CleanInc.  Make that change now.  Then, draw out a quick block diagram on paper and convince yourself that this is what you want.  That is, make sure that you have your code so that the INC input from the button goes into the clean module and that the output of that module (CleanInc) is now what drives the MUX select wire.
-Next, we need to create an XDC file for your design to declare the pin numbers for each top-level port of the design.  This lab is the first time you will be attaching a clock signal. You will need a **create_clock** command to declare the frequency of the clock (this is so the tools can ensure that the circuitry they produce can run at that rate). These commands are available in the master XDC file and can be used by uncommenting it in your project-specific XDC file.
-<code TCL>
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
-</code>
-In addition, tie the CLR and INC signals to two different push buttons and tie the Q output bits to leds 3-0. From previous labs you should know how to do this.
-Perform the steps of Synthesis, Implementation, and Bitstream Generation. Download your design and demonstrate that it is working properly.  When you push CLR the count should go to 0.  When you push INC the counter should increment once.  Experiment with your counter long enough to convince yourself it really works.
-AWESOME!  You have designed your first sequential circuit.
-===== Final Pass Off =====
-Pass off your laboratory by demonstrating the following to the TA:
-  * Pass off Exercise 4 by showing it working on the board
-<color red>How many hours did you work on the lab?</color>
-<color red>Provide any suggestions for improving this lab in the future.</color>
-<color red>Submit your final SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards).
-===== Personal Exploration =====
-Here are some ideas for personal exploration in this laboratory:
-  * Make your counter wider and wire up to additional LEDs.
-  * Wire in a copy of your 7-segment decoder from last week and have the 4-bit counter value displayed on the 7-segment display.  By the way, this is way cooler than just making your counter wider...
-<color red>Describe your personal exploration activities.</color>
-/*
-===== Lab Report =====
-  * **Header**
-    * Class
-    * Lab
-    * Name
-    * Section
-  * **Preliminary**
-    * Q waveform
-  * **Exercise 1**
-    * Simulation screenshot
-    * 4-bit register Verilog
-  * **Exercise 2**
-    * TCL script
-    * Register file Verilog
-  * **Exercise 3**
-    * Top-level Verilog
-  * **Exercise 4**
-    * Synthesis warnings
-    * Number of LUTs and FFs
-  * Personal exploration description
-  * Hours spent on lab
-  * Feedback
-*/
-----
-[[labs:ta:registerfile|TA Notes and Feedback]]

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