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labs:debounce [2020/03/16 15:19] nelson [Exercise #3 - Top-Level Push Button Counter] |
labs:debounce [2020/04/30 09:44] (current) nelson old revision restored (2020/03/11 14:27) |
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| - | ===== UNDER CONSTRUCTION ===== | ||
| - | This assignment is being modified in light of the change to on-line courses. This notice will be removed when this page is finalized for this semester. </color> | ||
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| ====== Debounce State Machine ====== | ====== Debounce State Machine ====== | ||
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| By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | ||
| - | <del>**Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.</del> \\ \\ | + | **Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.\\ \\ |
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| - | <del>**Exercise 3 Pass-off:** Show a TA your top level code and your tcl script. Your simulation must show the expected behavior of your debounce module.</del> | + | **Exercise 3 Pass-off:** Show a TA your top level code and your tcl script. Your simulation must show the expected behavior of your debounce module.\\ \\ |
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| - | **Exercise 3 Pass-off:** <color red>Attach your code and your Tcl script to the Lab Writeup page (there are locations to do so). Your simulation must show the expected behavior of your debounce module. If you did not (previous to BYU's conversion to on-line classes) pass off the lab, this will take the place of the normal lab pass off score for this lab. If you had previously passed off to the TA's, you will keep the 100% score you already received for the pass off part of this lab (I looked - everybody who already had passed off had gotten 100% for the pass off).</color> | + | |
| ==== Exercise #4 - Implementation and Download ==== | ==== Exercise #4 - Implementation and Download ==== | ||
| - | <del> | + | |
| After successfully verifying your top-level module, create and add a .xdc file to the project and proceed with the implementation of your design. | After successfully verifying your top-level module, create and add a .xdc file to the project and proceed with the implementation of your design. | ||
| - | </del> | ||
| - | <del> | ||
| <color red>Provide a summary of your synthesis warnings</color>. | <color red>Provide a summary of your synthesis warnings</color>. | ||
| - | </del> | ||
| - | <del> | ||
| After successfully synthesizing your design, proceed with the implementation and bitstream generation of your design. | After successfully synthesizing your design, proceed with the implementation and bitstream generation of your design. | ||
| - | </del> | ||
| - | <del> | ||
| <color red>Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.</color> | <color red>Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.</color> | ||
| - | </del> | ||
| /* TODO: have them do a timing analysis on the circuit - this is the first fully synchronouos design */ | /* TODO: have them do a timing analysis on the circuit - this is the first fully synchronouos design */ | ||
| - | <del> | ||
| Once the bitstream has been generated, download your bitstream to verify that it works correctly. After downloading your circuit, press the button several times to see if you can see a difference between the counter using the debounce state machine and the counter that does not use the debug state machine. | Once the bitstream has been generated, download your bitstream to verify that it works correctly. After downloading your circuit, press the button several times to see if you can see a difference between the counter using the debounce state machine and the counter that does not use the debug state machine. | ||
| - | </del> | ||
| - | <del> | ||
| <color red>Summarize the results from your experiments comparing the debounced counter value to the non-debounced counter value.</color> | <color red>Summarize the results from your experiments comparing the debounced counter value to the non-debounced counter value.</color> | ||
| - | </del> | ||
| /* TODO: Could consider an oscilliscope exercise. Is the logic analyzer able to captuer a 10 ns pulse? */ | /* TODO: Could consider an oscilliscope exercise. Is the logic analyzer able to captuer a 10 ns pulse? */ | ||
