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labs:debounce [2019/10/29 09:48] jgoeders [Exercise #3 - Top-Level Push Button Counter] |
labs:debounce [2020/04/30 09:44] (current) nelson old revision restored (2020/03/11 14:27) |
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| Create your debounce FSM using behavior SystemVerilog. | Create your debounce FSM using behavior SystemVerilog. | ||
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| + | {{ :labs:debounce:debounce_sm.png?600 |}} | ||
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| + | The diagram above shows a ''clr'' signal that resets/initializes your state machine. You should use your ''reset'' input to set your state machine to S0. | ||
| ** Debounce Timer ** | ** Debounce Timer ** | ||
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| Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | ||
| */ | */ | ||
| - | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone" and then reset to 0. Your counter must also be cleared when clrTimer is asserted. | + | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone". Your counter should be cleared when clrTimer is asserted by the state machine. |
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| + | By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | ||
| **Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.\\ \\ | **Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.\\ \\ | ||
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| {{ :labs:tb_debounce.v |}} | {{ :labs:tb_debounce.v |}} | ||
| + | <color red>Include a copy of your testbench output in your lab report</color> | ||
| - | **Exercise 2 Pass-off:** Make sure the output of the testbench has no errors. You don't need to get a TA to pass this off.\\ \\ | + | **Exercise 2 Pass-off:** No passoff, just make sure that you passed the testbench with zero errors.\\ \\ |
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| An edge detector circuit can be implemented by feeding a signal through two flip-flops (F1, then F2) and then outputting the equation ''F1 AND F2'''. This is shown in Figure 26.5 of the textbook. | An edge detector circuit can be implemented by feeding a signal through two flip-flops (F1, then F2) and then outputting the equation ''F1 AND F2'''. This is shown in Figure 26.5 of the textbook. | ||
| - | 4. The final part of this circuit is a counter that counts the button transitions. Create a 16-bit counter with an enable input. Attach the enable signal to the output of the edge detection circuit. The output from the counter will be displayed on the seven segment display. Use the down button to clear this counter. | + | 4. The final part of this circuit is a counter that counts the button transitions. Create a 16-bit counter with an enable input. Attach the enable signal to the output of the edge detection circuit. The output from the counter will be displayed on the seven segment display. Use the reset intput to clear this counter. |
| ** Undebounced Counter ** | ** Undebounced Counter ** | ||
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| * Attach the 16-bit value of the //undebounced// counter to the upper 16 bits of the display | * Attach the 16-bit value of the //undebounced// counter to the upper 16 bits of the display | ||
| - | Your top-level design should look something like this: | + | Your top-level design should look something like this (clock, reset not shown): |
| - | {{:labs:debounce:lab_debounce.png?600|}} | + | |
| + | {{ :labs:debounce:lab_debounce.png?800 |}} | ||
| ** Simulation ** | ** Simulation ** | ||
