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labs:debounce [2019/07/17 15:30] jgoeders [Final Pass Off] |
labs:debounce [2020/04/30 09:44] (current) nelson old revision restored (2020/03/11 14:27) |
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
| + | | reset | Input | 1 | Active high reset | | ||
| | noisy | Input | 1 | Noisy debounce input | | | noisy | Input | 1 | Noisy debounce input | | ||
| | debounced | Output | 1 | Debounced output | | | debounced | Output | 1 | Debounced output | | ||
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| The inputs to the state machine are "noisy", which is a module input, and "timerDone", which is an internal signal. The outputs of the state machine are the signals "debounced", which is a module output, and an internal signal named "clrTimer". | The inputs to the state machine are "noisy", which is a module input, and "timerDone", which is an internal signal. The outputs of the state machine are the signals "debounced", which is a module output, and an internal signal named "clrTimer". | ||
| - | Create your debounce FSM using behavior SystemVerilog. Note that a large portion of code is given to you in Program 26.1.1. While this is a simple and straightforward approach, you will need to make some modifications to meet the given requirements. It is recommended that you create your module step-by-step without relying too heavily on what is already given. | + | Create your debounce FSM using behavior SystemVerilog. |
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| + | {{ :labs:debounce:debounce_sm.png?600 |}} | ||
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| + | The diagram above shows a ''clr'' signal that resets/initializes your state machine. You should use your ''reset'' input to set your state machine to S0. | ||
| ** Debounce Timer ** | ** Debounce Timer ** | ||
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| Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | Determine the size of this signal using the //clogb2// function and declare the counter signal by using the results of the //clogb2// function. | ||
| */ | */ | ||
| - | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone" and then reset to 0. Your counter must also be cleared when clrTimer is asserted. | + | The description of the debounce timer is found at the end of section 26.1. For this design, however, you will be required to wait precisely 5ms instead of whatever the maximum value for your timer is. At 5ms your timer should assert "timerDone". Your counter should be cleared when clrTimer is asserted by the state machine. |
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| + | By the way, if you have a parameterized counter from a previous lab, go ahead and use it - no need to re-invent the wheel. If not, you may choose to create a counter module parameterized for both maximum count value as well as bit-width (you will be needing such a counter in essentially every lab you complete moving forward). | ||
| **Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.\\ \\ | **Exercise 1 Pass-off:** Show a TA your debounce module. Explain how you implemented the state machine and how the state machine should behave when it receives a noisy input.\\ \\ | ||
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| {{ :labs:tb_debounce.v |}} | {{ :labs:tb_debounce.v |}} | ||
| + | <color red>Include a copy of your testbench output in your lab report</color> | ||
| - | **Exercise 2 Pass-off:** Show a TA your tcl script and the output of the testbench.\\ \\ | + | **Exercise 2 Pass-off:** No passoff, just make sure that you passed the testbench with zero errors.\\ \\ |
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| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
| + | | CPU_RESETN | Input | 1 | Active low reset | | ||
| | btnc | Input | 1 | Counter button input | | | btnc | Input | 1 | Counter button input | | ||
| - | | btnd | Input | 1 | Counter reset input | | ||
| | anode | Output | 8 | Seven Segment Display anode outputs | | | anode | Output | 8 | Seven Segment Display anode outputs | | ||
| | segment | Output | 8 | Seven Segment Display cathode segment outputs | | | segment | Output | 8 | Seven Segment Display cathode segment outputs | | ||
| Line 131: | Line 140: | ||
| The first section of this module will include the debounce state machine and a counter. The purpose of this circuit is to accurately count the number of times a button has been pressed. Although this function sounds simple, it takes some effort to create a circuit to reliably count button presses. As shown in the figure below, there are four components associated with this section of the circuit: | The first section of this module will include the debounce state machine and a counter. The purpose of this circuit is to accurately count the number of times a button has been pressed. Although this function sounds simple, it takes some effort to create a circuit to reliably count button presses. As shown in the figure below, there are four components associated with this section of the circuit: | ||
| - | * Synchronizer | + | - Synchronizer |
| - | * Debounce State Machine | + | - Debounce State Machine |
| - | * One-Shot pulse detector | + | - One-Shot pulse detector |
| - | * Counter | + | - Counter |
| {{ :labs:debounce_counter.png?500&nolink |}} | {{ :labs:debounce_counter.png?500&nolink |}} | ||
| - | The first first part of this circuit is the "synchronizer" whose purpose is to synchronize the asynchronous button signal to the global system clock. Because this signal is not synchronized to the clock, it is possible that this signal could cause metastability on later circuitry including the debounce state machine. You should use two flip-flops to synchronize this signal as described in section 24.3 (the textbook uses only one flip-flop - you will need to use two because of the 100 MHz clock rate). | + | 1. The first first part of this circuit is the "synchronizer" whose purpose is to synchronize the asynchronous button signal to the global system clock. Because this signal is not synchronized to the clock, it is possible that this signal could cause metastability on later circuitry including the debounce state machine. You can synchronize the signal by feeding it through two flip flips, as described in section 24.3 (the textbook uses only one flip-flop - you will need to use two because of the 100 MHz clock rate). \\ |
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| + | 2. Instance the your ''debounce'' state machine and attach the output of the synchronizer to the input of your state machine. The output of your state machine is now a synchronized, debounced version of the button input. | ||
| - | The second part of this circuit is the debounce state machine. Instance the your state machine and attach the output of the synchronizer to the input of your state machine. The output of your state machine is now a synchronized, debounced version of the button input. | + | 3. Add the "edge detector" circuit. The purpose of this circuit is to create a single clock cycle pulse when the debounced button signal transitions from a zero to a one. This single clock cycle pulse will be used to increment the button counter. If you attach the output of the debounce state machine directly into the input of your counter, the counter will increment continuously for as long as the button is pressed. The edge detector is added to make sure that the counter is only incremented once each time the button goes through a 0->1 transition. |
| - | The third part of this circuit is an "edge detector" circuit. The purpose of this circuit is to create a single clock cycle pulse when the debounced button signal transitions from a zero to a one. This single clock cycle pulse will be used to increment the button counter. If you attach the output of the debounce state machine directly into the input of your counter, the counter will increment continuously for as long as the button is pressed. The edge detector is added to make sure that the counter is only incremented once each time the button goes through a 0->1 transition. | + | An edge detector circuit can be implemented by feeding a signal through two flip-flops (F1, then F2) and then outputting the equation ''F1 AND F2'''. This is shown in Figure 26.5 of the textbook. |
| - | An edge detector circuit can be implemented as a simple Mealy state machine as shown below. This state machine has two states: S0 and S1. In state S0, the state machine is waiting for a '1' on the input and will generate a '1' on the edge output on the transition from S0 to S1. In the S1 state, the state machine is waiting for a '0' on the input. | + | 4. The final part of this circuit is a counter that counts the button transitions. Create a 16-bit counter with an enable input. Attach the enable signal to the output of the edge detection circuit. The output from the counter will be displayed on the seven segment display. Use the reset intput to clear this counter. |
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| - | {{ :labs:edge_detect.png?200&nolink |}} | + | |
| - | + | ||
| - | Note that this is the same thing as Figure 26.5, just represented in a different way. | + | |
| - | + | ||
| - | Implement this edge detection circuit within your top level module. | + | |
| - | + | ||
| - | The final part of this circuit is a counter that counts the button transitions. Create a 16-bit counter with an enable input. Attach the enable signal to the output of the edge detection circuit. The output from the counter will be displayed on the seven segment display. Use the down button to clear this counter. | + | |
| ** Undebounced Counter ** | ** Undebounced Counter ** | ||
| - | To demonstrate the behavior of the debounce circuit, a second counter is added to the top-level design which is incremented using a signal that is //not// debounced. The behavior of this counter will be contrasted with the debounced counter. You will use btnc as the input, btnd to clear, an edge detector, and a 16-bit counter, but you will not use a synchronizer or a debouncer. | + | To demonstrate the behavior of the debounce circuit, a second counter is added to the top-level design which is incremented using a signal that is //not// debounced. The behavior of this counter will be contrasted with the debounced counter. You will use btnc as the input, the reset signal to clear, an edge detector, and a 16-bit counter, but you will not use a synchronizer or a debouncer. |
| {{ :labs:nodebounce_counter.png?450&nolink |}} | {{ :labs:nodebounce_counter.png?450&nolink |}} | ||
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| ** Seven Segment Display ** | ** Seven Segment Display ** | ||
| - | After creating your two button counters, instance your seven segment display and connect the seven segment display as described below: | + | After creating your two button counters, instance the [[resources:seven_seg|Seven Segment Controller]] and connect the seven segment display as described below: |
| * You will use all 8 digits of the display | * You will use all 8 digits of the display | ||
| * Do not turn on any digit points | * Do not turn on any digit points | ||
| * Attach the 16-bit value of the //debounced// counter to the lower 16 bits of the display | * Attach the 16-bit value of the //debounced// counter to the lower 16 bits of the display | ||
| * Attach the 16-bit value of the //undebounced// counter to the upper 16 bits of the display | * Attach the 16-bit value of the //undebounced// counter to the upper 16 bits of the display | ||
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| + | Your top-level design should look something like this (clock, reset not shown): | ||
| + | |||
| + | {{ :labs:debounce:lab_debounce.png?800 |}} | ||
| ** Simulation ** | ** Simulation ** | ||
