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labs:codebreaker [2020/03/16 15:52] nelson [Personal Exploration] |
labs:codebreaker [2020/06/08 09:29] (current) nelson |
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| - | <color red> | ||
| - | ===== UNDER CONSTRUCTION ===== \\ | ||
| - | This assignment is being modified in light of the change to on-line courses. This notice will be removed when this page is finalized for this semester. \\ \\ | ||
| - | |||
| - | NOTE: changes have been made to the lab below. Items you no longer are required to do are shown with a <del>strikethrough</del>. | ||
| - | </color> | ||
| - | |||
| ====== Codebreaker ====== | ====== Codebreaker ====== | ||
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| Look over the top-level module, and make sure you understand how it works. The module contains: | Look over the top-level module, and make sure you understand how it works. The module contains: | ||
| - | * A ''clk_generator'' instance, that generates a 25MHz clock needed by the VGA display. | + | * A ''clk_generator'' instance, that generates a 25MHz clock needed by the VGA display. |
| * A ''BitmapToVga'' instance, that controls the VGA outputs, and has inputs that allow you to modify the pixel colors of the bitmap that is displayed over VGA. | * A ''BitmapToVga'' instance, that controls the VGA outputs, and has inputs that allow you to modify the pixel colors of the bitmap that is displayed over VGA. | ||
| * A ''CharDrawer'' instance, that is connected to the ''BitmapToVga'', that is used to draw messages to the bitmap, and thus the VGA display. | * A ''CharDrawer'' instance, that is connected to the ''BitmapToVga'', that is used to draw messages to the bitmap, and thus the VGA display. | ||
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| - Create an appropriate constraints file for all of the top-level ports. | - Create an appropriate constraints file for all of the top-level ports. | ||
| - Add all other necessary modules to your project. You will need to expand the modules in the Design Sources list to make sure you have included all necessary modules. For this lab, you only need to create the ''Codebreaker'' module (ports listed below). All other modules have been given to you, or were created in previous labs. | - Add all other necessary modules to your project. You will need to expand the modules in the Design Sources list to make sure you have included all necessary modules. For this lab, you only need to create the ''Codebreaker'' module (ports listed below). All other modules have been given to you, or were created in previous labs. | ||
| - | - <del>In this first exercise, your Codebreaker module will be very simple:</del> | + | - In this first exercise, your Codebreaker module will be very simple: |
| - | - <del>Drive the ''key_display'' and ''stopwatch_run'' outputs to 0.</del> | + | - Drive the ''key_display'' and ''stopwatch_run'' outputs to 0. |
| - | - <del>Drive the ''plaintext_to_draw'' output to a message of your choice to draw on the screen (the ''CharDrawer'' can only draw upper case letters, digits and spaces. </del> | + | - Drive the ''plaintext_to_draw'' output to a message of your choice to draw on the screen (the ''CharDrawer'' can only draw upper case letters, digits and spaces. |
| - | - <del>Connect the ''draw_plaintext'' output to the ''start'' input.</del> | + | - Connect the ''draw_plaintext'' output to the ''start'' input. |
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| - | <del>**Pass-off:** Generate the bitstream and program the board. You can use the **+** button on the monitors in the lab to switch them to the VGA input. Verify that your message is displayed after you press ''btnc''. You don't need to show it to the TAs.</del> | + | **Pass-off:** Generate the bitstream and program the board. You can use the **+** button on the monitors in the lab to switch them to the VGA input. Verify that your message is displayed after you press ''btnc''. You don't need to show it to the TAs. |
| ---- | ---- | ||
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| * It is good to choose meaningful state names (not S1, S2, etc.) This will help you reason about and debug your state machine. | * It is good to choose meaningful state names (not S1, S2, etc.) This will help you reason about and debug your state machine. | ||
| - | **Pass-off**: Show the TA your state machine and get feedback. | + | **Pass-off**: Show the TA your state machine. |
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| - | Implement your state machine in your ''Codebreaker'' module. Test your design with the following 128-bit cyphertext and 24-bit key. You should get a readable message <del>on the display</del> in your simulation. | + | Implement your state machine in your ''Codebreaker'' module. Test your design with the following 128-bit cyphertext and 24-bit key. You should get a readable message on the display. |
| <code SystemVerilog> | <code SystemVerilog> | ||
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| Use simulation to debug your design when necessary. | Use simulation to debug your design when necessary. | ||
| - | <del>For this exercise you can continue to connect 0 to the ''key_display'' and ''stopwatch_run'' outputs. Since your state machine is now assigning a value to ''draw_plaintext'', make sure you don't still have it connected to the ''start'' input.</del> | + | For this exercise you can continue to connect 0 to the ''key_display'' and ''stopwatch_run'' outputs. Since your state machine is now assigning a value to ''draw_plaintext'', make sure you don't still have it connected to the ''start'' input. |
| - | **Pass-off:** <del>Show the TA the decoded message being displayed on the monitor.</del> <color red> Include a screenshot of the simulation showing the decoded message in the lab report.</color> | + | **Pass-off:** Show the TA the decoded message being displayed on the monitor. |
| ---- | ---- | ||
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| - | <del>Test</del> Simulate your brute-force design on the cyphertext and key from the last exercise. Use simulation when necessary to help debug your design. | + | Test your brute-force design on the cyphertext and key from the last exercise. Use simulation when necessary to help debug your design. |
| - | <color red> Include a screenshot of your simulation waveforms demonstrating that your simulation works and finds the correct key (be sure both the key and resulting decoded text are visible in the simulation).</color> | ||
| - | **Final Pass-Off:** Choose one of the cyphertexts below, decode the message, and <del>display it on the VGA display</del> demonstrate that it works via simulation. NOTE: the cyphertexts were encoded using a key fairly close to 0 to minimize simulation time. Thus, if your search has not found the key prior to it reaching the value of 20, then you have a problem in your design and you can kill the simulation and start debugging your design. | + | **Final Pass-Off:** Chose one of the cyphertexts below, decode the message, and display it on the VGA display. |
| <code Verilog> | <code Verilog> | ||
| Line 248: | Line 240: | ||
| */ | */ | ||
| + | /* | ||
| + | <code Verilog> | ||
| + | assign cyphertext = 128'hca91b1577f34443894de1001885d6aa5; | ||
| + | assign cyphertext = 128'h57e967f1e86498a1eedc596a84f1fa26; | ||
| + | assign cyphertext = 128'h5b99cbef5dffe0f58c3e81df23ba858f; | ||
| + | assign cyphertext = 128'h77c58ceb8e5b342a583db6be53f8097c; | ||
| + | assign cyphertext = 128'hbd6a2012369d963f18802a8a70ca7ec7; | ||
| + | </code> | ||
| + | */ | ||
| + | /* Small keys for simulation: | ||
| + | "BRUTE FORCE RC4" key = 24'h000009; | ||
| + | "EZ KEY IS 000003" key = 24'h000003; | ||
| + | "THAT TOOK FORVER" key = 24'h000013; | ||
| + | " I PICKED NUM 4 " key = 24'h000004; | ||
| + | "YOU CRACK ME UP " key = 24'h000007; | ||
| + | */ | ||
| <color red>Submit your ''Codebreaker'' SystemVerilog module using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | <color red>Submit your ''Codebreaker'' SystemVerilog module using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
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| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
| - | * <del>Try creating your own encrypted message. You can use [[https://cryptii.com/pipes/rc4-encryption]]. Set the mode to encode, be sure your input string is 16 characters and your key is 3 bytes. Keep in mind, the byte order of the key is reversed; for example, if you choose a key of "AABBCC" on the website, the resulting key will be 24'hCCBBAA in the SystemVerilog implementation. The plaintext/cyphertext doesn't need to be re-ordered.</del> | + | * Try creating your own encrypted message. You can use [[https://cryptii.com/pipes/rc4-encryption]]. Set the mode to encode, be sure your input string is 16 characters and your key is 3 bytes. Keep in mind, the byte order of the key is reversed; for example, if you choose a key of "AABBCC" on the website, the resulting key will be 24'hCCBBAA in the SystemVerilog implementation. The plaintext/cyphertext doesn't need to be re-ordered. |
| - | * <del>Look through the ''CharDrawer'' SystemVerilog module and explore how it works. </del> | + | * Look through the ''CharDrawer'' SystemVerilog module and explore how it works. |
| - | * <del>Look through the RC4 decryption module, and see how it implements the algorithm described on the RC4 Wikipedia page.</del> | + | * Look through the RC4 decryption module, and see how it implements the algorithm described on the RC4 Wikipedia page. |
| - | * <del>Move the message to be drawn in a different location on the screen, and change the color.</del> | + | * Move the message to be drawn in a different location on the screen, and change the color. |
| - | * <del>**Challenge:** Speed up the brute-force algorithm by using 2 or 4 simultaneous RC4 decryption instances, and have each of them try a different part of the key space. Stop as soon as any of the modules find the correct key.</del> | + | * **Challenge:** Speed up the brute-force algorithm by using 2 or 4 simultaneous RC4 decryption instances, and have each of them try a different part of the key space. Stop as soon as any of the modules find the correct key. |
