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labs:codebreaker [2020/03/16 15:40] nelson |
labs:codebreaker [2020/06/08 09:29] (current) nelson |
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| - | <color red> | ||
| - | ===== UNDER CONSTRUCTION ===== \\ | ||
| - | This assignment is being modified in light of the change to on-line courses. This notice will be removed when this page is finalized for this semester. \\ \\ | ||
| - | |||
| - | NOTE: changes have been made to the lab below. Items you no longer are required to do are shown with a <del>strikethrough</del>. | ||
| - | </color> | ||
| - | |||
| ====== Codebreaker ====== | ====== Codebreaker ====== | ||
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| Look over the top-level module, and make sure you understand how it works. The module contains: | Look over the top-level module, and make sure you understand how it works. The module contains: | ||
| - | * A ''clk_generator'' instance, that generates a 25MHz clock needed by the VGA display. | + | * A ''clk_generator'' instance, that generates a 25MHz clock needed by the VGA display. |
| * A ''BitmapToVga'' instance, that controls the VGA outputs, and has inputs that allow you to modify the pixel colors of the bitmap that is displayed over VGA. | * A ''BitmapToVga'' instance, that controls the VGA outputs, and has inputs that allow you to modify the pixel colors of the bitmap that is displayed over VGA. | ||
| * A ''CharDrawer'' instance, that is connected to the ''BitmapToVga'', that is used to draw messages to the bitmap, and thus the VGA display. | * A ''CharDrawer'' instance, that is connected to the ''BitmapToVga'', that is used to draw messages to the bitmap, and thus the VGA display. | ||
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| - Create an appropriate constraints file for all of the top-level ports. | - Create an appropriate constraints file for all of the top-level ports. | ||
| - Add all other necessary modules to your project. You will need to expand the modules in the Design Sources list to make sure you have included all necessary modules. For this lab, you only need to create the ''Codebreaker'' module (ports listed below). All other modules have been given to you, or were created in previous labs. | - Add all other necessary modules to your project. You will need to expand the modules in the Design Sources list to make sure you have included all necessary modules. For this lab, you only need to create the ''Codebreaker'' module (ports listed below). All other modules have been given to you, or were created in previous labs. | ||
| - | - <del>In this first exercise, your Codebreaker module will be very simple:</del> | + | - In this first exercise, your Codebreaker module will be very simple: |
| - | - <del>Drive the ''key_display'' and ''stopwatch_run'' outputs to 0.</del> | + | - Drive the ''key_display'' and ''stopwatch_run'' outputs to 0. |
| - | - <del>Drive the ''plaintext_to_draw'' output to a message of your choice to draw on the screen (the ''CharDrawer'' can only draw upper case letters, digits and spaces. </del> | + | - Drive the ''plaintext_to_draw'' output to a message of your choice to draw on the screen (the ''CharDrawer'' can only draw upper case letters, digits and spaces. |
| - | - <del>Connect the ''draw_plaintext'' output to the ''start'' input.</del> | + | - Connect the ''draw_plaintext'' output to the ''start'' input. |
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| */ | */ | ||
| + | /* | ||
| + | <code Verilog> | ||
| + | assign cyphertext = 128'hca91b1577f34443894de1001885d6aa5; | ||
| + | assign cyphertext = 128'h57e967f1e86498a1eedc596a84f1fa26; | ||
| + | assign cyphertext = 128'h5b99cbef5dffe0f58c3e81df23ba858f; | ||
| + | assign cyphertext = 128'h77c58ceb8e5b342a583db6be53f8097c; | ||
| + | assign cyphertext = 128'hbd6a2012369d963f18802a8a70ca7ec7; | ||
| + | </code> | ||
| + | */ | ||
| + | /* Small keys for simulation: | ||
| + | "BRUTE FORCE RC4" key = 24'h000009; | ||
| + | "EZ KEY IS 000003" key = 24'h000003; | ||
| + | "THAT TOOK FORVER" key = 24'h000013; | ||
| + | " I PICKED NUM 4 " key = 24'h000004; | ||
| + | "YOU CRACK ME UP " key = 24'h000007; | ||
| + | */ | ||
| <color red>Submit your ''Codebreaker'' SystemVerilog module using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | <color red>Submit your ''Codebreaker'' SystemVerilog module using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
