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labs:arithmetic [2019/07/17 15:08] jgoeders [Final Pass Off] |
labs:arithmetic [2020/02/07 16:53] (current) nelson [Exercise #1 - 9-bit Binary Adder] |
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| Unlike the previous laboratory assignment, this laboratory will involve **hierarchy**. This is covered in-depth in Chapter 11, but will be briefly explained here. | Unlike the previous laboratory assignment, this laboratory will involve **hierarchy**. This is covered in-depth in Chapter 11, but will be briefly explained here. | ||
| - | A circuit with hierarchy is a circuit that contains modules within modules. In many complex digital logic circuits there are many levels of hierarchy. In this circuit you will have three levels of hierarchy - your FullAdd, your Add9, and a top level module. For this exercise you will create the Add9 which will **instance** 9 FullAdd modules. Program 11.1.1 gives an example of instancing modules. In this case, three "mux21" modules are instanced within the "mux41" module. | + | A circuit with hierarchy is a circuit that contains modules within modules. In many complex digital logic circuits there are many levels of hierarchy. In this circuit you will have three levels of hierarchy - your FullAdd, your Add9, and a top level module. For this exercise you will create the Add9 which will **instance** 9 FullAdd modules. Program 11.1.1 in your textbook gives an example of instancing modules. In this case, three "mux21" modules are instanced to build a "mux41" module. |
| The next step in this exercise is to create a 9 bit ripple-carry adder. Create a new SystemVerilog file named Add9.sv and add the following ports as shown in the table below: | The next step in this exercise is to create a 9 bit ripple-carry adder. Create a new SystemVerilog file named Add9.sv and add the following ports as shown in the table below: | ||
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| | co | Output | 1 | Carry out of last stage | | | co | Output | 1 | Carry out of last stage | | ||
| - | After creating the empty module, place 9 instances of your **FullAdd** module as described in Section 9.1 of the textbook and as shown in the figure below. | + | After creating the empty module, create the needed local wires (you will need some, figure out where), and insert 9 instances of your **FullAdd** module into your Add9 module (as described in Section 9.1 of the textbook and as shown in the figure below). You should use the .port(wire) way of mapping ports on instances to your wires (see Program 11.1.2 in the textbook). |
| - | Note that the **co** output of your Add9 is the carry-out of the last FullAdd instance. | + | Note that the **co** output of your Add9 is the carry-out of the last FullAdd instance. |
| {{ :labs:add9.png?650&nolink |}} | {{ :labs:add9.png?650&nolink |}} | ||
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| </code> | </code> | ||
| - | Read the following [[tutorials:tcl_tutorial_2|tutorial]]. This tutorial contains additional examples and instruction for creating TCL files. | + | Read the following [[tutorials:tcl_tutorial|tutorial]]. This tutorial contains additional examples and instruction for creating TCL files. |
