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labs:arithmetic [2018/10/03 10:13] wirthlin [Exercise #1 - 9-bit Binary Adder] |
labs:arithmetic [2020/02/07 16:53] (current) nelson [Exercise #1 - 9-bit Binary Adder] |
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| <color red> | <color red> | ||
| Extend each of the following numbers to nine bits using //sign-extension//: | Extend each of the following numbers to nine bits using //sign-extension//: | ||
| - | </color> (Note that sign extension is described in section 3.3.3 of the textbook) | + | </color> (Note that sign extension is described in section 3.3.1 of the textbook) |
| * 10000100 | * 10000100 | ||
| * 00011001 | * 00011001 | ||
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| === 1-bit Full Adder === | === 1-bit Full Adder === | ||
| - | Start by creating a new Vivado project for this lab. Next, create an empty SystemVerilog file named "FullAdd.sv" and add the following ports to this module as described in the table below: | + | Start by creating a [[tutorials:vivado_project_setup|new Vivado project]] for this lab. Make sure you follow the steps in red to properly configure the error messages in your project. Next, create an empty SystemVerilog file named "FullAdd.sv" and add the following ports to this module as described in the table below: |
| ^ Module Name: FullAdd ^^^^ | ^ Module Name: FullAdd ^^^^ | ||
| Line 113: | Line 113: | ||
| <color red>Include a copy of your full adder TCL simulation script in your lab report.</color> | <color red>Include a copy of your full adder TCL simulation script in your lab report.</color> | ||
| - | <color red>Include a copy of your full adder SystemVerilog code in your lab report.</color> | ||
| === 9-Bit Adder === | === 9-Bit Adder === | ||
| Line 119: | Line 118: | ||
| Unlike the previous laboratory assignment, this laboratory will involve **hierarchy**. This is covered in-depth in Chapter 11, but will be briefly explained here. | Unlike the previous laboratory assignment, this laboratory will involve **hierarchy**. This is covered in-depth in Chapter 11, but will be briefly explained here. | ||
| - | A circuit with hierarchy is a circuit that contains modules within modules. In many complex digital logic circuits there are many levels of hierarchy. In this circuit you will have three levels of hierarchy - your FullAdd, your Add9, and a top level module. For this exercise you will create the Add9 which will **instance** 9 FullAdd modules. Program 11.1.1 gives an example of instancing modules. In this case, three "mux21" modules are instanced within the "mux41" module. | + | A circuit with hierarchy is a circuit that contains modules within modules. In many complex digital logic circuits there are many levels of hierarchy. In this circuit you will have three levels of hierarchy - your FullAdd, your Add9, and a top level module. For this exercise you will create the Add9 which will **instance** 9 FullAdd modules. Program 11.1.1 in your textbook gives an example of instancing modules. In this case, three "mux21" modules are instanced to build a "mux41" module. |
| The next step in this exercise is to create a 9 bit ripple-carry adder. Create a new SystemVerilog file named Add9.sv and add the following ports as shown in the table below: | The next step in this exercise is to create a 9 bit ripple-carry adder. Create a new SystemVerilog file named Add9.sv and add the following ports as shown in the table below: | ||
| Line 131: | Line 130: | ||
| | co | Output | 1 | Carry out of last stage | | | co | Output | 1 | Carry out of last stage | | ||
| - | After creating the empty module, place 9 instances of your **FullAdd** module as described in Section 9.1 of the textbook and as shown in the figure below. | + | After creating the empty module, create the needed local wires (you will need some, figure out where), and insert 9 instances of your **FullAdd** module into your Add9 module (as described in Section 9.1 of the textbook and as shown in the figure below). You should use the .port(wire) way of mapping ports on instances to your wires (see Program 11.1.2 in the textbook). |
| - | Note that the **co** output of your Add9 is the carry-out of the last FullAdd instance. | + | Note that the **co** output of your Add9 is the carry-out of the last FullAdd instance. |
| {{ :labs:add9.png?650&nolink |}} | {{ :labs:add9.png?650&nolink |}} | ||
| Line 143: | Line 142: | ||
| </code> | </code> | ||
| - | The following [[tutorials:tcl_tutorial_2|tutorial]] contains additional examples and instruction for creating TCL files. | + | Read the following [[tutorials:tcl_tutorial|tutorial]]. This tutorial contains additional examples and instruction for creating TCL files. |
| <color red>Include a copy of your 9-bit adder TCL simulation script in your lab report.</color> | <color red>Include a copy of your 9-bit adder TCL simulation script in your lab report.</color> | ||
| - | <color red>Include a copy of your 9-bit full adder SystemVerilog code in your lab report.</color> | + | |
| + | |||
| + | **Exercise 1 Pass-off:** Show a TA your simulation for your Add9 module and explain how you know your circuit is correct. Also, show that your tcl script for the FullAdd module tested all possible combinations.\\ \\ | ||
| ==== Exercise #2 - Top-Level Design ==== | ==== Exercise #2 - Top-Level Design ==== | ||
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| <color red>Copy the testbench output from the TCL console to your lab report. </color> | <color red>Copy the testbench output from the TCL console to your lab report. </color> | ||
| - | <color red>Include your top-level SystemVerilog code in your lab report.</color> | + | |
| + | **Exercise 2 Pass-off:** Show a TA your top level code and explain how you connected the inputs to your Add9 module. Also, show that the testbench did not report any errors.\\ \\ | ||
| ==== Exercise #3 - Synthesize, Implement and Download ==== | ==== Exercise #3 - Synthesize, Implement and Download ==== | ||
| Line 237: | Line 239: | ||
| Perform the [[tutorials:bitgen]] step. Download your circuit and verify that it works as expected. | Perform the [[tutorials:bitgen]] step. Download your circuit and verify that it works as expected. | ||
| - | ===== Personal Exploration ===== | ||
| - | Here are some ideas for personal exploration in this laboratory: | + | ===== Final Pass Off ===== |
| - | * Create a one's complement circuit (simulation or download) | + | |
| - | * Modify the behavior of the buttons | + | |
| - | * Learn more about the simulation environment and tools | + | |
| - | <color red>Describe your personal exploration activities.</color> | + | The following are required for pass off: |
| - | ===== Pass Off ===== | + | * Completed pass offs for Exercise 1 and 2 |
| - | + | ||
| - | Demonstrate the following to a TA to pass off your laboratory: | + | |
| - | * Your testbench simulation without any errors | + | |
| * Your working circuit on the Nexys4 board | * Your working circuit on the Nexys4 board | ||
| Line 255: | Line 250: | ||
| <color red>Provide any suggestions for improving this lab in the future.</color> | <color red>Provide any suggestions for improving this lab in the future.</color> | ||
| + | |||
| + | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| + | |||
| + | ===== Personal Exploration ===== | ||
| + | |||
| + | Here are some ideas for personal exploration in this laboratory: | ||
| + | * Create a one's complement circuit (simulation or download) | ||
| + | * Modify the behavior of the buttons | ||
| + | * Learn more about the simulation environment and tools | ||
| + | |||
| + | <color red>Describe your personal exploration activities.</color> | ||
| /* | /* | ||
