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lab_grading [2019/05/02 14:12] jgoeders [Coding Standard Grading] |
lab_grading [2019/09/10 15:24] (current) jgoeders [Coding Standard Grading] |
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| * Each lab grade will be broken down into: | * Each lab grade will be broken down into: | ||
| * 80% pass-off | * 80% pass-off | ||
| - | * 10% online lab report, submitted through Learning Suite (20% for Lab 1 and 2) | + | * 20% online lab report, submitted through Learning Suite |
| - | * 10% adherence to coding standard, source code submitted through Learning Suite (0% for Lab 1 and 2, which don't contain SystemVerilog code) | + | * For labs where you submit your SystemVerilog code (all labs except 1 and 2), half of the online lab report grade will be based on your adherence to coding standard. |
| ==== Coding Standard Grading ==== | ==== Coding Standard Grading ==== | ||
| - | The TAs will apply the following grading rubric when evaluating your SystemVerilog source code. The goal is to get you in the habit of writing, readable, reusable, high-quality code. As such the TAs will be quite strict when grading your code. | + | Read the [[verilog_coding_standards|SystemVerilog Coding Standard]]! |
| - | * You start out with 100% credit (10 points) for the code-quality part of your grade. | + | |
| - | * Each coding infraction reduces the code-quality credit by 1 point. Making the "same mistake multiple times" will still results in losing multiple points. (eg. if your ''always_comb'' is missing default values for multiple signals assigned in the block, you will be deducted 1 point for each signal that does not have a default value). | + | |
| - | * Your first 3 infractions are freebies. (ie. 5 infractions will results in a grade of 8/10) | + | |
| + | The TAs will apply the following grading rubric when evaluating your SystemVerilog source code. The goal is to get you in the habit of writing, readable, reusable, high-quality code. As such the TAs will be quite strict when grading your code. | ||
| + | * You start out with 100% credit (10 points) for the code-quality part of your grade. If the lab consists of submitting multiple SystemVerilog modules, they will be worth a combined 10 points (as indicated in LearningSuite). | ||
| + | * Each coding infraction reduces the code-quality credit by 1 point. Making the "same mistake multiple times" will result in losing multiple points. (eg. if your ''always_comb'' is missing default values for multiple signals assigned in the block, you will be deducted 1 point for each signal that does not have a default value). | ||
| + | | ||
