ECEn 220Table of Contents
This page contains an index to all of the tutorials in each of the labs. You will likely need to refer to these tutorials more than once as you complete the labs in the class.
Lab Getting Started
- Creating a CAEDM Account
- Instructions for Completing ECEN 220 Laboratory Assignments
- Using CAEDM Storage (J Drive)
- Printing to a CAEDM Printer
- Using the CAEDM Scanner
Lab Board Intro
- Basys 3 FPGA Board Overview (video)
- Setting Jumpers on the Basys 3 Board
- Downloading a bit file to the Basys 3 Board
- Downloading a bit file to the Basys 3 Board Using Adept
- Selecting the Display Video Input
Lab Structural SV
- Creating a New Vivado Project
- Adding a SystemVerilog Design Module to a Project
- Viewing SystemVerilog as a Schematic
- Starting the Vivado HDL Simulation Tool
- Tcl Tutorial 1
- Using Constraint Files (XDC)
- Adding a Constraints File to your Project
- Running the HDL Synthesis Tool
- Running the Implementation Design Step
- Running the Bitgen Design Step