ECEn 220
Tutorials Resources TA Hours SystemVerilog Coding Standard Lab Grading
Labs
Getting Started Board Intro Linux Intro Structural SV Arithmetic Seven Segment Fun With Registers Stopwatch Debouncer UART Transmitter Codebreaker UART Receiver
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Resources

Table of Contents

  • Tool Resources
  • Design Resources
  • Modules
  • Documentation

Tool Resources

  • Help Queue
  • Accessing Course CAD Tools
  • Testbenches - An Alternative to Tcl
  • Taming Vivado - Or, What to Do When Vivado Seems Broken?
  • Simulation Hints
  • Linux Command Summary

Design Resources

  • Constraints File: basys3_220.xdc
  • Combinational Logic Styles

Modules

  • Seven-Segment Controller
  • Bitmap to VGA

Documentation

  • Basys 3 Reference Manual
  • Basys 3 Schematics